OC65R1, Overclocking With Modified CRC65

This page documents my attempt to maximize CRC65's clock speed

The basic approach for maximizing clock frequency is to reduce loading and use fastest part. Loading is reduced by using DOM interface that is a direct wiring between DOM disk and CRC65's 44-pin IDE connector thus eliminated the compact flash adapter. For faster speed, 10 nS RAM is used instead of 25nS RAM, furthermore the RAM's chip select is permanenet enabled so RAM access is sped up. There is also a modification to the clock line to buffer output of oscillator with 74VLC1G14 but that does not seem to make any difference in maximum clock achieved. Because the RAM decoding has changed, the CPLD equations are modified to reflect the change. These modifications are done on a CRC65 rev2 PCB, 33MHz operation is achieved with these modifications.

Schematic is same as CRC65's schematic but RAM's chip select (pin 22) is grounded

CPLD equations

TeraTerm macro script file and associated software to initialize DOM disk of a 33MHz CRC65. Unzip files into c:\teraterm\oc65 and execute the macro file 'newDOS65CF_v3_33M_fast.ttl'