Partial Emulation of MC6850 ACIA

Introduction

When using the ACIA in the popular no-parity, 8-data, and 1 stop bit mode and when baud clock is integer multiple of system clock, the ACIA design simplifies significantly so it can be emulated with a small CPLD. This repurposed FRR512K board describes such emulation.

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Features

  • Serial port setting of 115200, 8-data, 1-stop, and no parity
  • Serial baud must be integer multiple of system clock
  • Implemented in EPM7064SLC44
  • Re-purposed FRR512K board

Design Information

CPLD design file

Engineering change

Interrupt

  • Flash-pin30 (Bank3) to T7 (nINT)

Serial Connections

  • SCL to serial hdr pin2 (TxD)
  • SDA to serial hdr pin3(RxD)
  • serial hdr pin5 to GND
  • serial hdr pin1 (nRTS) to flash-pin22(nROMCS)

Data bus connections

  • Flash-pin1 (Bank4) to Flash-pin 18 (D4)
  • Flash-pin2 (Bank2) to Flash-pin19(D5)
  • Flash-pin3(Bank1) to Flash-pin20(D6)

Components Populated

  • P1, RC2014 bus connector,
  • U1, EPM7064SLC44
  • P3, CPLD programming header
  • P21, 6-pin serial port header
  • U2, Oscillator
  • R1,R4, 4.7K resistors
  • 100 ohm resistor between T8 and T37
  • Bypass capacitors
builderpages/plasmo/frr512k/rev0/emul6850.txt · Last modified: 2021/12/18 10:57 by plasmo
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