Eazy80 Rev1

Rev1 PCB of Eazy80 corrected many errors in rev0 pc board.

• Z80 at 22 MHz
• Z84C90 with 2 serials, 4 timers and discrete I/O
• 128K RAM
• 64K PROM or EEPROM
• CP/M ready
• Three classic RC2014 expansion connectors
• 100mm X 100mm pc board
• No glue logic design

This is a classical microprocessor design with CPU, I/O, RAM and ROM but with one unusual feature: To keep the part count at minimal, both RAM and ROM are chip selected when Z80 is accessing the memory space. To boot up, only ROM's output enable is asserted at reset; In this mode RAM is selected but write-only; the first routine in ROM firmware is to read its own code and write it back into the same location; this unusual operation does not affect the read-only ROM, but duplicate the ROM program into the write-only RAM. When the duplication operation is completed, the firmware enable the RAM's output enable and disable ROM's output enable so now the program is running in RAM.

The RAM is 128K and its highest address is controlled by KIO output, PC0, which selects the low or high 64K bank of RAM. The ROM write operation mentioned above writes identical software to both high and low 64K bank of RAM such that when the RAM switches bank, the program execute the exact same program on the other bank, so the execution continue as if nothing has happened. The very top of each 64K bank ($FF00-$FFFF) contained a collection of bank-sharing routines. This is the mechanism to pass data between 2 banks of 64K RAM.

KIO has an independent serial clock so the processor clock can change without affecting the serial communication rate. In some cases, the CPU clock can be successfully overclocked to 30MHz by simply replacing the nominal 22MHz oscillator with 30MHz oscillator.

Schematic

Gerber photoplots

Bill of Materials

PCB assembly guide

EaZy80 monitor, this is Simple80 monitor rev0.92 with few changes tailored for EaZy80.

CP/M 2.2 for EaZy80, this is Simple80 CP/M22 BIOS with few changes.tailored for EaZy80.

Ladislau Szilagyi has enhanced HiTech C compiler to use the 2nd bank of 64K RAM. This enhancement allows larger C programs to be compiled. He also created an enhanced version of TE editor that uses the 2nd bank of 64K RAM to handle larger file. The TE editor itself is compiled using the enhanced HiTech C. The is the CF disk image that contains enhanced HiTech C, TE editor source codes, and compiled TE editor. Copy the unzipped image file to 64MB or larger CF disk using disk imaging tool like Win32DiskImager.

TE editor. This is the compiled TE editor mentioned above. Below is a screen shot of the editor in operation.

This project modifies rev1 Eazy80 pc board so it can accommodate 512K RAM with 16 banks of 32K RAM and a SD interface to run RomWBW. The first step of the modification is to wire in a 74hct32 (quad OR) in the uncommitted 14-pin DIP. The output of the quad OR gates are bank select that drive the 4 high addresses of 512K RAM so the low 32K of Z80 addresses (0x0-0x7FFF) is mapped to one of 15 banks. When high 32K of Z80 is accessed, it always maps to the highest bank, bank 0xF, of 512K RAM. The bank register is controlled by 4 discrete outputs of channel C of PIO, PC0, PC1, PC2, PC6. The second step of 512K RomWBW modifications is adding a SD card to PIO channel B so that PB3 is connected to SD's CS, PB4 is connected to SD's CLK, PB0 is connected to SD's MOSI, and PB7 is connected to SD's MISO.

Schematic of modified Eazy80 for 512K RomWBW

ROM monitor for modified Eazy80 for 512K RomWBW

Modification to RomWBW HBIOS.asm to accommodate Eazy80_512K banking scheme

Modification to RomWBW's SD.asm to accommodate different IO address.

SD card image for Eazy80 for 512K RomWBW

Eazy80_512K SD image is generated using “buildEAZY512.cmd” which invoke the “build.cmd” in “Eazy512” directory under RomWBW\Source. This zipped file contains the collection of .cmd and files needed to make Eazy80_512K SD image

Engineering changes for modified Eazy80 for 512K RomWBW

The engineering changes for adding SD card is described here.