Table of Contents
CRC65, A Frugal 6502 Single Board Computer
CRC65 stands for CPLD, RAM, CFdisk, and 6502. It is a very simple single board computer using CF disk to store system and application programs. Its simplicity allows it to run quite fast, yet fit in an economical 2-layer pc board. Discussion about CRC65 can be found here: http://forum.6502.org/viewtopic.php?f=10&t=6440
This is link to the first prototype of CRC65
This is link to Rev2 of CRC65 that can accommodate either W65C02 or W65C816
- W65C02 operating at 14.7MHz
- CY7C109 RAM provides 58K of RAM space
- Altera EPM7064S CPLD with the following features
- 64-byte boot ROM
- Double-buffered serial receiver at 115200 N81
- Software bit-bang transmitter operating at 115200 N81
- Compact Flash interface
- I2C interface
- RAM decode
- Bus-connected IDE44 interface.
- Modified RC2014 expansion bus
- 50mm x 100mm 2-layer pc board
Theory of Operation
Altera EPM7064S or its equivalent Atmel ATF1504AS is the heart of CRC65. It provides 64 bytes of boot ROM located at the top of 6502's memory space. The boot ROM has two modes of operations:
- CF bootstrap, where it loads the content of CF's Master Boot Record into memory at 0xB000 and execute. This is the normal mode of opertion.
- Serial bootstrap, where it loads 256 bytes of serial binary data into memory at 0xB000 and execute. Serial bootstrap mode is mainly used to initialize a new CF disk to load the system and application software.
At the negation of reset, the boot ROM alternately polls serial receive ready flag or CF disk busy flag. Because CF disk typically need 1/2 second to negate its busy flag, the user can enter the serial bootstrap mode by enter a key immediately after the reset button is released. If the serial port has received an input, the boot ROM will discard the first character received and sit in a loop waiting for 256 serial binary data. The data are saved in RAM starting from location 0xB000 up to 0xB0FF. When the 256th data is received, the program execution starts at 0xB000.
CPLD design file
- Interim CPLD design for improved CF disk access. With faster CF disks, this CPLD design can support CRC65 overclocked to 29.5MHz.
- Schematic of Interim CPLD design in PDF format
Memory map of CRC65
Engineering Change for rev0 pcb
Signal definition of modified RC2014 expansion bus
CFBootloader is a collection of utility software for loading software in designated locations in CF disk. This is beta version of CFBoot:
- Run from 0xb17c to copy CF bootstrap code into CF's Master Boot Record
- Load CRCMon.hex and run from 0xb1d9 to copy CRCMon into CF
- Load Memtest.hex and run from 0xb250 to copy memory test into CF
- Load min_mon.hex and run from 0xb2b3 to copy EhBASIC into CF.
CRCMon, a simple monitor for CRC65, rev0.8c.
Conway's Game of Life driving 128×64 OLED display over I2C bus. Program starts at 0xa000
Clock simulates traditional clock movement. Program starts at 0x1000
Manuals and Instruction
Boards for CRC65
I2C Daughter boards
128×64 OLED display. The commerical 4-pin 128×64 OLED display can be plugged directly into CRC65's I2C interface.
RTC prototype board based on PCF8563 plugs into CRC65 I2C interface and generate periodic interrupt to CRC65.
LED Display board
CPLDTIL board is modified to be compatible with CRC65's expansion bus.
SPI prototype board based on 65SPI
Daryl Rictor's 65SPI is prototyped with ProtoRC3 and functioned as an expansion board for CRC65.