Table of Contents
lynchaj project page for Z80 Multi Board Computer (aka Z80 Modular Backplane Computer)
The purpose of this project is to revisit the design concepts behind original Z80 SBC (aka test prototype) which has evolved into the SBC V2-005 over several years. Attempt to introduce some new concepts to make the design more modular, flexible, and less expensive. Use low cost prototype PCBs (100x100mm) available for less than $20 including shipping from JLCPCB. Make simple single function boards to implement good program design concepts from Computer Science: high cohesion and low coupling. Maintain as much backward compatibility with latest SBC V2 as possible.
The Z80 MBC consists of four core boards: Z80 backplane, Z80 processor, Z80 clock, and Z80 ROM. These are sufficient to build a working system of minimum capability. However even the core boards are designed in such a way that they can be individually redesigned and replaced with improved designs and/or customized to suit the builder. It achieves low coupling by implementing a simple bus using off-the-shelf 2×25 2.54mm spaced pin headers and socket strips. The backplane is a replication of a fully buffered Z80 CPU pin out in the same order with 10 spare pins reserved for customization. Each board has high cohesion by being limited to a single function consisting of only parts specifically related to to perform its task. This lowers builder cost by eliminating unnecessary parts and improves system reliability by having fewer parts to fail. Likewise, if a component or whole board fails it can be replaced without affecting the remaining boards.
Additional Design Goals
There are several additional design goals for the Z80 MBC.
First, is to ease constraints on the design to allow for some new configurations. Specifically capability to access memory over the bus and configurable memory map holes for external memory.
A second design goal is making all IO devices optional, fully configurable, and limiting IO port addresses to only the minimum necessary. Multiple IO devices can exist in the system simultaneously or not exist as the builder chooses. Lowers cost and improves system reliability by removing unneeded and/or unwanted capabilities.
The third design goal is allowing multiple memory modules with boot enable jumpers to specify boot devices present after CPU reset.
Fourth, adding simple debug features like user LEDs and a switch.
Fifth, implementing a fully buffered Z80 processor with configurable wait state capability and no internal IO or memory devices. Related is each board is also fully buffered to keep bus signals only on the bus with no raw bus signals intruding into the board past the buffers.
Sixth, maintain backwards compatibility to the extent possible (two exceptions so far) to reuse existing SBC software. Target software is current ROMWBW
Seventh, lower build cost by using inexpensive off-the-shelf components and PCBs. All parts come from Jameco or ordered off eBay (bus connectors). Use simple 9vdc 1A unregulated power supply. Keep part count on boards low so they are effectively disposable eliminating the need for sockets and further lowering builder costs. Make non-essential components optionally do-not-populate.
Areas For Improvement
- correct LED orientation on silkscreen
- add component labels on silkscreen
- add 3-pin bypass jumper to optionally allow 7805 voltage regulator/Pololu 5V regulator *or* the use of external 5V DC regulated, center positive power supply
- add power switch or use in-line switch on power cable
- orient power LED to vertical
- allocate 10 spare bus pins to
- spare0 to GND
- spare1 to VCC
- spare2 to IEI#
- spare3 to IEO#
- spare4 to BAI#
- spare5 to BAO#
- spare6 to DREQ#
- spare7 to TEND#
- spare8 to i2c TX
- spare9 to i2c RX
- add 20 pin extended bus lines connector to 4 of 8 slots. Include 8 more data lines, 8 more address lines, another GND, and VCC plus 2 undefined spares
- change LM7805 TO-220 footprint to improve thermal management (vias and/or heatsink)
- add screw terminal power block
- add more slots (8 → 20)
Z80 processor: (fixed in V2)
correct LED and diode orientation on silkscreen add component labels on silkscreen add local oscillator for CPU clock and selector circuit to allow for use of local oscillator or clock signal from bus connector for CPU add clock to bus jumper add IM 2 external interrupt circuit add mounting bracket holes and exclusion zones
Z80 clock: (fixed in V2)
correct LED and diode orientation on silkscreen add component labels on silkscreen selection jumper for battery back up fix IO port address decoder logic exchange USER0 and USER1 LEDs to be in more logical order for debugging; USER1 on the right and USER0 on the left add clock to bus jumper
Z80 clock V2
- add 10K ohm resistor in parallel with piezo speaker to fix low volume issue
- add component labels on silkscreen
- MPCL select LED?
- Add 3 pin jumper for pin 3 of ROM to select VCC or A15 to better support 28 pin EPROM
- Add mounting holes and exclusion zones
- Move LEDs to top of board
Z80 serial: (fixed in V2)
move power LED to left most position and move chip select LED to the right one reposition U3 label add inverters to TX/RX LEDs (active high) add user button on Ring Indicator on UART for ROMWBW recovery mode rename UART oscillator clock P3 to a U* designator add over-the-top external DMA connector remove female 6 pin TTL serial header add mounting bracket holes & exclusion zones
Z80 RAM (fixed in V2)
fix broken DS1210 circuitry, connect to RAM0 and RAM1 chip selects add mounting holes and exclusion zones
Z80 serial V2
- convert DIP-40 16C550 to PLCC format
- R12 pin 1 connected to ground instead of VCC causing power LED to not work. Fix is to disconnect R12, pin 1 and connect to pin immediately to its right (VCC)
Z80 Prototyping board:
- socket footprints too close together causing interference preventing install. Work around is to directly solder in ICs in a couple of sockets to free up some room
Z80 RAM V2
- Add tolerance jumpers for DS1210s (5% or 10%)
Z80 backplane PCB partially assembled during testing
Z80 processor partially assembled during testing
Z80 processor and backplane during testing
Z80 clock during build and test
Z80 ROM board, initial build and test
First boot, running jploop. Run/Halt LED is green, CPU is running. Also ROM0 chip select LED lit
More testing, with halt ROM. Run/Halt LED is red. CPU is halted. ROM0 chip select lit
Z80 serial board build and test
Z80 serial board, running scream test ROM. This is major milestone when something goes from being a collection of parts to an actual computer. Not quite there yet but big steps towards it
Z80 RAM partial build, starting test and check out.
Z80 backplane, Z80 processor, Z80 clock, Z80 ROM, Z80 serial, and Z80 RAM board all running CP/M 2.2
Z80 MBC with DSKY next generation with Z80 PPIDE in action
Z80 FDC partial build, starting test and check out.
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