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If you started your Multicomp journey with Grante Searle's web page, then you would have started with one or more AS6C1008 chips. If you progressed from the original point to point soldering setup to the Multicomp PCB you will now find yourself with a PCB capable of supporting two RAM chips.

However, the Multicomp IIc does not support 2 x 128kb chips. It is designed to use the following memory options:

  • 1 x 128kb RAM (AS6C1008) ; or
  • 1 x 512kb RAM (AS6C4008); or
  • 2 x 512kb RAM (2xAS6C4008).

The following documentation describes my effort to configure the Multicomp to access the two 128Kb RAM chips as a contiguous block of 256Kb.

The memory configuration on the Multicomp is controlled by a set of three jumpers and these configure the address lines to set these three configurations:

  • A16 Jumper
  • A17 Jumper
  • A18 Jumper

These jumpers only affect the configuration of RAM chip one. RAM chip two is has all address lines connected directly to the FPGA.

The limitation with using 128Kb chips is that that A17 and A18 address line connections on the chip perform different functions on the 128Kb chip:

  • A17 is a secondary chip enable.
  • A18 is not connected.

So, if you have two 128Kb chips, the Multicomp will not recognize the second chip and configure it as a contiguous block.

How to use 2x128Kb chips of your Multicomp IIc:

Code changes required:

In the CycloneIIc.vhd file make these two changes:

1) Under Cyclone IIc entity add:

   CHIPOE        : out std_logic:='1';

2) Under CHIP SELECTS GO HERE SECTION change

n_externalRam1CS<= not(n_RomCS and n_internalRam1CS and not physicaladdr(19));
n_externalRam2CS<= not(n_RomCS and n_internalRam1CS and physicaladdr(19));

to

n_externalRam1CS<= not(n_RomCS and n_internalRam1CS and not physicaladdr(17));
n_externalRam2CS<= not(n_RomCS and n_internalRam1CS and physicaladdr(17));

Make the following two change to the pin configurations using the Pin Assignment Editor:

1) Disable the A17 address line output to PIN_31

sramAddress[17] Location PIN_31 Enabled = No

2) Create a new output to drive PIN_31 on permanently.

CHIPOE Location PIN_31 Enabled = Yes

Configure the Jumpers

  • A16 Jumper 2-3 - Connect FGPA pin 25 address line A16 to pin 2 of RAM chip 1 which is the chips A16 address line.
  • A17 Jumper 2-3 - Connect FPGA pin 31 which is the new CHIPOE high signal to RAM chip one pin 30 which is the secondary chip enable.
  • A18 Jumper 2-3 - Connect FPGA pin 32 address line A18 to pin 1 of RAM chip one which is an unused pin.

www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_b1ackmai1er_images_jumpers.jpg

After these three sets of changes have been done, recompile and program your Multicomp.

I have tested this configuration using the Debug Monitor by writing to different banks and the chip enable and mapping appears to work correctly.

What this gives you:

  • An address range 0-0x40000 which the MMU sees as a contiguous block mapped as 16 x 16kb blocks 0 - 15.
  • Under the Debug Monitor 5 banks of 48Kb mapped across that range:
    • Bank 0 - block 0, 1, 2 + 3 (common block - Debug Monitor)
    • Bank 1 - block 4, 5, 6 + 3 (common block - Debug Monitor)
    • Bank 2 - block 7, 8, 9 + 3 (common block - Debug Monitor)
    • Bank 3 - block 10, 11, 12 + 3 (common block - Debug Monitor)
    • Bank 4 - block 13, 14, 15 + 3 (common block - Debug Monitor)

The remaining limitation is the the CP/M, CP/M 3 and MP/M software is unable to dynamically recognize this memory configuration.

Thanks to the assistance of Max Scane and Rienk and of course Grant Searle for his original work.

builderpages/b1ackmai1er/start.1513423669.txt.gz · Last modified: 2017/12/16 06:27 by b1ackmai1er
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