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--- boards:sbc:tiny68k [2018/01/09 15:27]
plasmo
+++ boards:sbc:tiny68k [2020/06/28 19:31] (current)
plasmo old revision restored (2019/09/07 13:42)
@@ Line 75: / Line 75: @@
   * 11/23/17 update: The original design files posted were incorrect. This is the correct version of the design files. Altera EPM7128 {{:boards:sbc:tiny68k:released_version_nov2017.zip|design files}}  Designs are created in Quartus 8.1, should be compatible with later version of Quartus. Designs are entirely in schematics. {{:boards:sbc:tiny68k:tiny68k_epm7128_release.pdf|Schematic in PDF}}  format. {{:boards:sbc:tiny68k:released_epm7128_program_binary.zip|Programming binary}}  in .pof format.
-  * 11/14/17 update of the EPM128 design file. The original design has 1 wait state for DRAM access. This is not necessary for 8-12MHz system clock. The performance is improve by about 20% moving from 1 wait state access to 0 wait state access.. Also a minor fix for CF's IORD & IOWR signals so they are asserted only when CF's chip select is asserted. Original design works just fine, this fix is merely helping with hardware debugging instrumentation. Here is the EPM7128 {{:boards:sbc:tiny68k:tiny68k_epm7128_zero_wait.zip|Zero Wait state design}}  file. {{:boards:sbc:tiny68k:tiny68k_epm7128_zero_wait.pdf|Zero Wait state schematic}}  in PDF format. Zero wait state {{:boards:sbc:tiny68k:tiny68k_epm7128_zero_wait_program_binary.zip|programming binary}}  in .pof format.
+  * <del>11/14/17 update of the EPM128 design file. The original design has 1 wait state for DRAM access. This is not necessary for 8-12MHz system clock. The performance is improve by about 20% moving from 1 wait state access to 0 wait state access.. Also a minor fix for CF's IORD & IOWR signals so they are asserted only when CF's chip select is asserted. Original design works just fine, this fix is merely helping with hardware debugging instrumentation. Here is the EPM7128 {{:boards:sbc:tiny68k:tiny68k_epm7128_zero_wait.zip|Zero Wait state design}}  file. {{:boards:sbc:tiny68k:tiny68k_epm7128_zero_wait.pdf|Zero Wait state schematic}}  in PDF format. Zero wait state {{:boards:sbc:tiny68k:tiny68k_epm7128_zero_wait_program_binary.zip|programming binary}}  in .pof format.</del>
 CP/M-68K {{:boards:sbc:tiny68k:tinybios_r4.zip|BIOS}}  for Tiny68K
-  * 11/14/17 updated {{:boards:sbc:tiny68k:tinybios_r5.zip|BIOS rev 5}}, console input is passed to CP/M unaltered.
+  * <del>11/14/17 updated {{:boards:sbc:tiny68k:tinybios_r5.zip|BIOS rev 5}}, console input is passed to CP/M unaltered.</del>
+  * 3/20/18 updated {{:boards:sbc:tiny68k:tinybios_r6.zip|BIOS rev 6}}, fix setexec routine so trace exception is installed.
 CP/M-68K {{:boards:sbc:tiny68k:cpm15000.zip|CPM v1.3}}
@@ Line 91: / Line 92: @@
   * Memory diagnostics
   * {{:boards:sbc:tiny68k:clrcpmmem.zip|Clear CP/M memory}}  area
+  * {{:boards:sbc:tiny68k:tstssd1306.zip|tstSSD1306}}. By removing AT24C256 from U7 and ground pin U7-7 to U7-4, a 128×64 OLED I2C display can be plugged into the socket. tstSSD1306 is the program to write the ASCII table to the OLED display.
 ===== Board build procedures =====
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 ==== Potential problem with reading CF disk ====
-Certain brands of CF disks may not work on some Tiny68K rev 1 board. This is a [[:boards:sbc:tiny68k:rev1_CF_problem|write up]] about this problem and possible solutions.
+Certain brands of CF disks may not work on some Tiny68K rev 1 board. This is a [[:boards:sbc:tiny68k:rev1_cf_problem|write up]] about this problem and possible solutions.