Tiny68K, 68000 SBC

Introduction

Tiny68K is a high-performance yet low-cost single board computer based on the Motorola 68000. Tiny68K has two unusual features:

  • The entire 16-megabyte memory space of 68000 (except the top 32Kbyte of I/O space) is filled with RAM,
  • The boot software residesin a 32Kbyte serial flash that is copied into the lowest 32Kbyte of the DRAM when powered up or with a reset. The RAM-resident boot software can be modified just like any data in RAM but is overwritten on the next power cycle or with a reset.

Figure below shows an assembled Tiny68K.

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Features

  • Motorola 68000 CPU
  • MC68681 DUART, port A is the console operating at 38400 baud, 8N1, with CTS/RTS hardware handshake.
  • Altera EPM7128 CPLD contains the glue logics:
    • State machine to load 32K serial flash when powered up or with a reset,
    • DRAM controller for a 16-megabyte SIMM72 DRAM module,
    • Hidden CAS-before-RAS refresh in hardware, no software overhead required,
    • memory decoder,
    • Interrupt controller,
    • Bus Error watchdog timer,
  • 8-16 MHz 0scillator (only 8 MHz operation is tested)
  • 32Kbyte serial flash, 24C256 as the boot device.
  • Second 32K serial flash that can be programmed in situ and serves as the boot device with just one jumper change.
  • 44-pin edge connector interfaces to a low-cost IDE-CF module
  • SIMM72 socket to accommodate a 16-megabyte SIMM DRAM module
  • SIMM72 expansion port (currently not tested)
  • 7-segment LED display as visual indicator of board operations.
  • Target for CP/M-68K ver 1.3
  • 100mm x 100mm 2-layer pc board
  • 5V operation

Descriptions

Low cost without sacrificing performance is the design goall of Tiny68K. Cost control is achieved by:

  • Two-layer PC board in 100mm x 100mm format. Many board manufacturers only charge 50 cents per board in quantity of 10 in this format,
  • Memory in the form of surplused 72-pin SIMM 16-megabyte DRAM modules. Such modules can be purchased for $2-3 each on eBay,
  • Low cost 5-Volt CPLD, Altera EPM7128, that is about $2-3 each from China,
  • Use low-cost serial flash memory as the boot memory,
  • Interface via pc board edge connector to a low-cost 44-pin IDE-CF module,
  • No on-board RS232 transceiver because most USB-based serial port modules operate at the TTL level.

Good performance is maintained by:

  • 16-bit wide data bus,
  • 16-megabyte SIMM72 DRAM operating at zero wait state (at 8MHz system clock),
  • Fast serial flash loads monitor in 0.6 second after a reset or power on,
  • 16-bit wide bus-connected IDE interface operating with zero wait state at 8MHz,
  • Hidden CAS-before-RAS refresh cycle with no software overhead.

Memory map

  • RAM is from 0x0 to 0xFF7FFF,
  • Serial Flash is from 0xFFD000-0xFFDFFF
  • IDE-CF is from 0xFFE000-0xFFEFFF
  • 68681 DUART is from 0xFFF000-0xFFFFFF

Design Files

Rev 1 schematic

Rev 1 Gerber files

Part list

Tiny68K Monitor debugger. The software is developed in the EASy68K tool chain. Programming binary for serial EEPROM programmer (CH341).

Altera EPM7128 design files Designs are created in Quartus 8.1, should be compatible with later version of Quartus. Designs are entirely in schematics. Schematic in PDF format. Programming binary in .pof format.

  • 11/23/17 update: The original design files posted were incorrect. This is the correct version of the design files. Altera EPM7128 design files Designs are created in Quartus 8.1, should be compatible with later version of Quartus. Designs are entirely in schematics. Schematic in PDF format. Programming binary in .pof format.
  • 11/14/17 update of the EPM128 design file. The original design has 1 wait state for DRAM access. This is not necessary for 8-12MHz system clock. The performance is improve by about 20% moving from 1 wait state access to 0 wait state access.. Also a minor fix for CF's IORD & IOWR signals so they are asserted only when CF's chip select is asserted. Original design works just fine, this fix is merely helping with hardware debugging instrumentation. Here is the EPM7128 Zero Wait state design file. Zero Wait state schematic in PDF format. Zero wait state programming binary in .pof format.

CP/M-68K BIOS for Tiny68K

  • 11/14/17 updated BIOS rev 5, console input is passed to CP/M unaltered.

CP/M-68K CPM v1.3

CP/M-68K v1.3 distribution disk image for Tiny68K RAMdrive

RS232 adapter board to interface to the DB9 serial connector of a PC. The RS232 adapter is not needed for most USB-to-serial adapters which have TTL level I/O.

Utility

Board build procedures

Build procedure for Tiny68K Kit #1 (building from scratch)

Build procedure of partially assembled board for Kit #2

Build procedure for Tiny68K Kit #2 (SMT capacitors and resistors already assembled, EPM7128 assembled and programmed).

Photo below is an annotated assembled board

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Operating Tiny68K

Connect to a PC

A PC with terminal program such as Hyperterminal is needed to interface with Tiny68K. An USB-to-serial adapter with TTL level input/output can connect directly to Tiny68K's console connector. For USB-to-serial adapter with RS232 I/O, an adapter board is needed.

Powering up Tiny68K

Apply 5V to the board via the 2.5mm power jack, the center is 5V, barrel is ground. The nominal power consumption at 8MHz system clock is 500mA. When powered is applied, the 7-segment LED will display '8' for a second and then '6'. While waiting for console command, the outer segments of the 7-segment display will flash for 1/2 second, one segment at a time, in a circular sequence. If the display indicate a static '4', it is waiting for hardware handshake signal to assert. Be sure the terminal program has RTS/CTS hardware handshake enabled.

Creating a new CF disk

Procedure for creating a new CF disk

boards/sbc/tiny68k.txt · Last modified: 2017/11/28 09:32 by plasmo
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