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boards:sbc:sbc_v2:start [2019/01/07 10:18]
b1ackmai1er [Memory Paging]
boards:sbc:sbc_v2:start [2019/01/13 20:56] (current)
b1ackmai1er [Port Map]
Line 219: Line 219:
 ===== Port Map ===== ===== Port Map =====
  
-PPI 82C55 I/O 60-67+The SBC V2 uses address 60h - 7Fh for on board peripherals. Address decoding is not complete so some address ports are duplicated within this address range. All other I/O address ranges are exported to the ECB.
  
-16550 UART $68+^Peripheral^Function^Address| 
 +|82C55 PPI|Parallel Port|60h-63h ( & 64h-67h)| 
 +|16550 UART|Serial Port|68h-6Fh| 
 +|DS1302 RTC|Real Time Clock|70h ( & 71h-77h)| 
 +|RAM|RAM bank select latch (Write Only)|78h ( & 79h)| 
 +|ROM|ROM bank select latch (Write Only)|7Ch ( & 7Eh)|
  
-RTC LATCH AND INPUT PORT $70 +\\
- +
-RAM MEMORY PAGER CONFIG LATCH - RAM (WRITE ONLY) $78 +
- +
-RAM MEMORY PAGER CONFIG LATCH - ROM (WRITE ONLY) $7C+
  
  
boards/sbc/sbc_v2/start.txt · Last modified: 2019/01/13 20:56 by b1ackmai1er
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