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boards:sbc:sbc_v2:start [2018/07/13 05:21]
b1ackmai1er [Serial Cable Instructions]
boards:sbc:sbc_v2:start [2019/01/13 20:56] (current)
b1ackmai1er [Port Map]
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 {{https://​www.retrobrewcomputers.org/​lib/​plugins/​ckgedit/​fckeditor/​userfiles/​image/​boards/​sbc/​sbc_v2/​photos/​img_1112a.jpg?​nolink&​600x450|www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_boards_sbc_sbc_v2_photos_img_1112a.jpg}} {{https://​www.retrobrewcomputers.org/​lib/​plugins/​ckgedit/​fckeditor/​userfiles/​image/​boards/​sbc/​sbc_v2/​photos/​img_1112a.jpg?​nolink&​600x450|www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_boards_sbc_sbc_v2_photos_img_1112a.jpg}}
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 [[https://​www.retrobrewcomputers.org/​lib/​exe/​fetch.php?​tok=0e9afb&​media=https://​www.retrobrewcomputers.org/​lib/​plugins/​ckgedit/​fckeditor/​userfiles/​image/​boards/​sbc/​sbc_v2/​sbc-v2-003-brd.png|{{https://​www.retrobrewcomputers.org/​lib/​plugins/​ckgedit/​fckeditor/​userfiles/​image/​boards/​sbc/​sbc_v2/​sbc-v2-003-brd.png?​direct&​652x408}}]] [[https://​www.retrobrewcomputers.org/​lib/​exe/​fetch.php?​tok=0e9afb&​media=https://​www.retrobrewcomputers.org/​lib/​plugins/​ckgedit/​fckeditor/​userfiles/​image/​boards/​sbc/​sbc_v2/​sbc-v2-003-brd.png|{{https://​www.retrobrewcomputers.org/​lib/​plugins/​ckgedit/​fckeditor/​userfiles/​image/​boards/​sbc/​sbc_v2/​sbc-v2-003-brd.png?​direct&​652x408}}]]
 +===== Errata =====
 +There is an error in the board layouts of sbc-v2-003 compared to the original schematic that results in the external reset not working in Kontron mode.
 +To configure the board to work in Kontron mode with the external reset coming from the backplane the following workaround can be made.
 +  - Pin 3 on K13 needs to be jumpered to Pin 2 of P6 (Reset switch jumper) - this connects the backplane reset input pin (c31) to the reset circuit input.
 +  - Pin 1-2 needs to be jumpered on K13 - this connects the /reset circuit output to the backplane reset out pin(c26).
 ===== Jumper Settings ===== ===== Jumper Settings =====
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 8Mhz CPU Crystal - 57600 baud 8Mhz CPU Crystal - 57600 baud
-Baud rate can be changed using the CP/M MODE program i.e. MODE COM0:​57600,​8,​N,​1 /P+Baud rate can be changed using the CP/M MODE program i.e. [[:​software:​firmwareos:​romwbw:​apps|MODE ]]COM0:​57600,​8,​N,​1 /P
-If garbled characters are seen on the display ​for serial file transfers fail, a lower baud rate should be tried.+If garbled characters are seen on the display ​or serial file transfers fail, a lower baud rate should be tried.
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 The utility can also set and read the RTC memory. The utility can also set and read the RTC memory.
-RTC.COM is part of Wayne Warthen'​s [[https://​github.com/​wwarthen/​RomWBW|ROMWBW]] package.+[[:​software:​firmwareos:​romwbw:​apps|RTC.COM ​]]is part of Wayne Warthen'​s [[https://​github.com/​wwarthen/​RomWBW|ROMWBW]] package. 
 ===== Status LED ===== ===== Status LED =====
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 </​code>​ </​code>​
-===== Changes from V1 =====+===== Memory Paging ​=====
-Information regarding V1 can be found [[:​boards:​sbc:​sbc_v2:​sbc_v1|here.]]+The SBC can be configured with 128Kb or 512Kb RAM and up to 512Kb ROM. The Z80 processor can only access 64Kb at one time, so the additionally memory is accessed through a memory paging scheme.
-\\+The memory paging system can be configured in two different ways but the default is to be set with 32Kb of RAM fixed at the top 8000h-FFFFh memory range and for the bottom 32Kb 0000h-7FFFh being selectable from either the RAM or ROM chips. This 32Kb/32Kb configuration is what is supported by the ROMWBW software package.
 +Under the 32Kb/32Kb configuration,​ the top 32Kb is mapped to the last 32Kb of the 128Kb or 512Kb RAM chip and the lower 32Kb is selected from RAM or ROM by writing the required address line configuration to the RAM or ROM memory page configuration latch.
-===== Parts List =====+===== One Bit Input Port =====
-Full list of parts:​{{:​boards:​sbc:​sbc_v2:​sbc-v2-parts-list.pdf|:​boards:​sbc:​sbc_v2:​sbc-v2-parts-list.pdf}}+Bit 6 of RTC port $70 is connect to an on board jumper JP2 which can be read by softwareBy default it is tied high. Removing jumper JP2 will result in the being tied low (=0).
-See [[:​boards:​sbc:​sbc_v2:​minimum-build|here]] ​for minimum build and parts substitution guidelines.+Effectively this creates a configurable jumper setting which the ROMWBW bootrom can use for determining the primary communications console.
-===== Software =====+This facility is not enabled by default in ROMWBW and the setting is ignored. To enable, rebuild the ROMWBW package with the CRTACT setting set to true. The CRT type can also be configured at this time:
-There is extensive firmware support for the SBC V2 and associated ECB peripheral cards. Currently there are two firmware builds still being actively developed - UNA and ROMWBW.+<font inherit/​Courier New,​Courier,​monospace;;​inherit;;​inherit>​SBC_std_cust.asm</​font>​
-See [[:​software:​firmwareos:​start#​active_projects|here]] for current software builds and information on historical projects.+<​code>​ 
-A debug boot ROM can be installed for testing - try James Moxham'​s ROMIMAGE.BIN from [[:​software:​firmwareos:​jm:​start|here]].+This will cause ROMWBW to check the status of BIT 6 at startupIf "​0"​ (jumper removed) it will change the primary communications console ​from the Serial UART to the first CRT console found. If a CRT console is not found it will default back to the Serial UART. If BIT 6 = "​1"​ (jumper in place) it will boot as normal with the primary console using the Serial UART.
-{{https://​www.retrobrewcomputers.org/​lib/​plugins/​ckgedit/​fckeditor/​userfiles/​image/​boards/​sbc/​sbc_v2/​romimage.png?​direct&​467x384}}+===== Boot "​BEEP"​ modification =====
-==== REAL TIME CLOCK (RTC====+There is no inbuilt sound on the SBC V2 board. Complex sound output can be achieved with the ECB-SCG ​(Sprite-Colour-Graphicsboard.
-The DS1302 real time clock can be set under CP/M using the **rtc** utility program. +Rudimentary sound support ​can be add the SBC V2 by utilizing one of the unused outputs of the RTC interfacing latch and connecting a simple amplifier to this output.
-<​code>​ +
-Loading CPM... +
-CP/M-80 Version 2.2C for the N8VEM, October 2008 +
-Run XM from A drive, ​this downloads file to B drive +
-A>rtc +
-Start RTC Program +
-RTC: Version 1.+
-RTC: Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut H)elp +
-RTC: trickle charger disabled. +
-RTC> +
-Set the time and date with the** //Init// **command first and then use the //​**Set**// ​ command ​to program it.+On U18 74LS174 connect a ground wire from pin 8 and a signal wire from pin 2 to an amplifier. Generic LM386 amplifiers are available from many sources and work well.
-RTC.COM can also be used to set up trickle charging for the backup battery or super capacitor if connected. More Information ​on charging Super Capacitors can be found here: [[https://​www.maximintegrated.com/​en/​design/​tools/​calculators/​product-design/​supercap.cfm|https://​www.maximintegrated.com/​en/​design/​tools/​calculators/​product-design/​supercap.cfm]]+With this addition and the ''​SPKENABLE''​ setting set to ''​TRUE ''​in ROMWBW, ​the SBC V2 will issue a beep sound on bootup.
-The utility can also set and read the RTC memory.+{{https://​www.retrobrewcomputers.org/​lib/​plugins/​ckgedit/​fckeditor/​userfiles/​image/​boards/​sbc/​sbc_v2/​sbc-v2-beep-mod.png?​nolink&​800 ​ }}
-RTC.COM is part of Wayne Warthen'​s [[https://​github.com/​wwarthen/​RomWBW|ROMWBW]] package. 
-===== Status LED =====+===== Port Map =====
-A single color or bicolor LED can be installed ​for the status LED. The LED monitors the status of the HALT line from the Z80 CPU. Consider the color selection and orientation when choosing. A red/green LED is ideal and logically should show green when cpu is running and red when halted. Or in the case of a single colour LED, on when cpu is running and off when haltedIt is wise to not fully solder in the LED until the orientation has been checked ​to confirm ​the right sequenceOr, you could install a pin header and run flying leads to an LED mounted in a case,+The SBC V2 uses address 60h - 7Fh for on board peripheralsAddress decoding ​is not complete so some address ports are duplicated within this address range. All other I/O address ranges are exported ​to the ECB.
-The HALT status can be initiated by booting CP/M and running the DDTZ debugger, loading and executing a HALT instruction.+^Peripheral^Function^Address| 
 +|82C55 PPI|Parallel Port|60h-63h ( & 64h-67h)| 
 +|16550 UART|Serial Port|68h-6Fh| 
 +|DS1302 RTC|Real Time Clock|70h ( & 71h-77h)| 
 +|RAM|RAM bank select latch (Write Only)|78h ( & 79h)| 
 +|ROM|ROM bank select latch (Write Only)|7Ch ( & 7Eh)|
-<​code>​ +\\
-B>ddtz +
-DDTZ v2.7M by CB Falconer. CPU=Z80 +
--a100 +
-0100   hlt +
-0101 +
--g100 +
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 Information regarding V1 can be found [[:​boards:​sbc:​sbc_v2:​sbc_v1|here.]] Information regarding V1 can be found [[:​boards:​sbc:​sbc_v2:​sbc_v1|here.]]
boards/sbc/sbc_v2/start.1531473695.txt.gz · Last modified: 2018/07/13 05:21 by b1ackmai1er
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