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boards:sbc:ns32000 [2021/02/20 11:58]
jcoffman [NS32016 / NS32532 / NS32CG160 CPU Differences Noted]
boards:sbc:ns32000 [2022/01/13 14:58] (current)
jcoffman [NS32016 / NS32532 / NS32CG160 CPU Differences Noted]
Line 69: Line 69:
   - There either is no assembler support for the UPSR or USP registers as directly accessible in supervisor state. The SP registers may be diddled by toggling the S bit in the PSR in supervisor state, and the User PSR may be diddled during a RETT or RETI instruction.   - There either is no assembler support for the UPSR or USP registers as directly accessible in supervisor state. The SP registers may be diddled by toggling the S bit in the PSR in supervisor state, and the User PSR may be diddled during a RETT or RETI instruction.
   - The 'CG160 has all the OEM peripherals: DMA & Timers.   - The 'CG160 has all the OEM peripherals: DMA & Timers.
-  - Interrupts are totally different on the 'CG160. <font inherit/inherit;;#e74c3c;;inherit>No NS32202</font> chip is usable. +  - Interrupts are totally different on the 'CG160. <font inherit/inherit;;#e74c3c;;inherit>No NS32202</font>  chip is usable. 
-  - The 'CG160 has a DE (Direct Exception) bit in the Configuration Register. This bit defeats the Module calling diring interrupts and traps. The NetBSD compiler doesn't support the module capability, anyhow.+  - The 'CG160 has a DE (Direct Exception) bit in the Configuration Register. This bit defeats the Module calling during interrupts and traps. The NetBSD compiler doesn't support the module capability, anyhow.
   - The 'CG160 has no MMU or CustomCoprocessor capability. The C & M bits in the configuration register instead control division of the input oscillator clock by 2, 4, 8 for power saving.   - The 'CG160 has no MMU or CustomCoprocessor capability. The C & M bits in the configuration register instead control division of the input oscillator clock by 2, 4, 8 for power saving.
  
boards/sbc/ns32000.txt · Last modified: 2022/01/13 14:58 by jcoffman
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