Table of Contents
Multicomp Papilio Duo (Xilinx Spartan-6)
“By downloading these files you must agree to the following: The original copyright owners of ROM contents are respectfully acknowledged. Use of the contents of any file within your own projects is permitted freely, but any publishing of material containing whole or part of any file distributed here, or derived from the work that I have done here will contain an acknowledgement back to myself, Grant Searle, and a link back to this page. Any file published or distributed that contains all or part of any file from this page must be made available free of charge.” -http://searle.hostei.com/grant/Multicomp/index.html, retrieved 12/14/15.
Welcome to my recently completed Project using the awesome Papilio Duo platform with the Classic Computing Shield (Xilinx Spartan 6). It's a migration of Grant Searle's brillant work called MULTICOMP, consisting in a flexible FPGA based architecture for implementing old style 8 bit Retro-computers using Z80, 6502 & 6809 “Soft-core” CPU's. You can take a look at the original Project, based on an Altera Cyclone II dev board, following this link: (Link to Grant's web site)
I've built the Z80 CP/M variant, complete with VGA & Keyboard terminal, Serial port, SD-Card and external SRAM. The steps I followed to accomplish this:
1. Adapted the pinouts, ports and some signals of all the modules (Main Interconect, Z80, VGA, Serial, Keyboard, SD-Card) from the original design to fully use the Computing Shield peripherals and the DUO's SRAM (using and updated Computing Shield UCF file).
2. Converted the original 6 bit color VGA to 12 bit color interface.
2. Converted the internal BIOS ROM and Character Font ROMs, to use Xilinx's Core Generator's Block Memory instead of the original Altera Altsyncram IP.
3. Converted the internal double port Display & Attribute RAMs also to use the Core Generator's Block Memory instead of the original Altera Altsyncram IP.
4. In my first attempt I adapter the CPU and Baudrate clock generators, to use the Papilio's 32 MHzOSC instead of the original 50 MHz, but I ran into timing problems converting the many clock -dependant constants in the design. So I decided to generate a new 50 MHzclock using the DCM & PLL Wizard.
Wherever possible I tried to maintain Grant's original VHDL & Z80 code, generating new signals and “wrapper” code to adapt to the different hardware. This way you can still refer to the original design as a rich learning experience, as every source code is available and well explained in Grant's website.
The final outcome is a very usable and complete Z80 soft-core based machine, running Digital Research CP/M 2.2 OS. The modular design concept allows for extensive hacks and mods.
Hope you enjoy it !
Hardware & FPGA Bitstream Documentation
I've attached some pictures of my working system and the full VHDL ISE 14.7 Project tree files, including an already generated “bit” file for transferring it to the Papilio Duo with the Computing Shield attached (default serial port baudrate is 9600, 8N1 no handshake).
I've also included a ready to go SD card image (SD only, not SDHC for now, 1 or 2 GB) with all the CP/M partitioning work already done including a very comprehensive software collection courtesy of Oscar Vermeulen (drives A to D, Users 0 to 9).
Link to Project files:
Link to SD Card image with CP/M 2.2 Software Collection:
Please use this space to add any notes/comments on this board that don't fit into the above sections. (Periodically, these comments may be re-arranged to be better incorporated into a new revision of the wiki page.) Please sign your comments using the wiki “Insert Signature” feature! — — Andrew Bingham 2016/09/14 12:21