Differences

This shows you the differences between two versions of the page.

--- boards:sbc:65c816_ecb_sbc:65c816_ecb_sbc [2017/10/08 02:01]
danwerner
+++ boards:sbc:65c816_ecb_sbc:65c816_ecb_sbc [2020/11/14 23:23] (current)
danwerner
@@ Line 1: / Line 1: @@
 ====== 65C816 ECB SBC ======
-{{  :boards:sbc:65c816_ecb_sbc:newboard.jpg?nolink&800x450  }}
+{{  :boards:sbc:65c816_ecb_sbc:newboard.jpg?nolink&800x450  |newboard.jpg}}
 ----
@@ Line 9: / Line 9: @@
 I will be adding more documentation to this page, as the project progresses – I hope to get firmware running on the board with support for the RBC disk controllers and Video adapters.
-For now, we have a ROM monitor working that supports the following commands:
+For now, we have a ROM monitor (based on Supermon 816– big thank you to BCS technology for making this software free to use/modify) working that supports the following commands:
 <code>
-REGISTER – Print CPU Registers
+A — Assemble code
-DUMP SSSS EEEE  -- dump ram from SSSS to EEEE
+C — Compare memory regions
-ENTER SSSS VV – enter value VV in address SSSS, will prompt for consecutive addresses until user responds with blank line
+D — Disassemble code
-GO SSSS – Run program at SSSS
+F — Fill memory region (cannot span banks)
-LOAD – load a S19 format file into memory
+G — Execute code (stops at BRK)
+H — Search (hunt) memory region
+J — Execute code as a subroutine (stops at BRK or RTS)
+L -- Load a Motorola format S28 file into memory
+M — Dump & display memory range
+R — Dump & display 65C816 registers
+T — Copy (transfer) memory region> — Modify up to 32 bytes of memory
+; — Modify 65C816 registers
 </code>
+I am working on building out hardware support in the BIOS. At the moment only on board Serial Read/Write, DISKIO V3 Floppy, VGA3 Video and PS/2 Keyboard and On board RTC is supported. The OS supports the FAT12 file system (8.3 file names) and will boot from a floppy disk. A ported version of 6502 ehBasic (emulation mode only) is also included in the software download.
+Long Term I intend to have support in the BIOS for:
+  * DISKIO V3 (HDD/FDD) **- Floppy interface working and supported by BIOS and OS, HDD and ATAPI interfaces in progress**
+  * VGA3 **- Supported in both Memory mapped and port access mode by both BIOS and OS**
+  * Dual SD – future
+  * DualDMA Disk (HDD/FDD) – future
+  * Color VDU – future
+  * VDU – future
+  * SCG – future
 The memory map is:
@@ Line 33: / Line 53: @@
 - 07FFFF On Board RAM
 - FFFFFF Open to ECB Bus
+Current BIOS functions are:
+Long Call:
+FF00 LOUTCH - output char in A to serial port
+FF03 LINCH - get char from serial port into A
+FF08 LINCHW - get char from serial port into A (Blocking)
+FF0C LINITDISK - initialize storage device (supports DISKIO V3 Floppy only at the moment)
+FF10 LREADDISK - Read Disk Sector into BIOS buffer (supports DISKIO V3 Floppy only at the moment)
+FF14 LWRITEDISK - write Disk Sector from BIOS buffer (supports DISKIO V3 Floppy only at the moment)
+FF18 LWRITERTC - Write value to RTC register
+FF1C LREADRTC - Read value from RTC register
+Short Call:
+FF71    OUTCH     - output char in A to serial port
+FF74    INCH      - get char from serial port into A
+FF77    INCHW     - get char from serial port into A (Blocking)
+FF7A    INITDISK  - initialize storage device (supports DISKIO V3 Floppy only at the moment)
+FF7D    READDISK  - Read Disk Sector into BIOS buffer (supports DISKIO V3 Floppy only at the moment)
+FF80    WRITEDISK - write Disk Sector from BIOS buffer (supports DISKIO V3 Floppy only at the moment)
+FF83    WRITERTC  - Write value to RTC register
+FF86    READRTC   - Read value from RTC register
 </code>
@@ Line 39: / Line 80: @@
 Note that while these tools do have a couple of bugs that require careful attention to syntax, they appear to be generally usable. Both an assembler and C compiler are available.
-the following commands will build the ROM: __'' ''__
+All of the source files as well as an assembled binary are in the ZIP file.
-<code>
-c:\wdc\tools\bin\wdc816as -L rom816.asm -O rom816.obj
-c:\wdc\tools\bin\wdcln -V -HI -T rom816.obj -O rom816.hex
-hex2bin -R32K -d 0 -s 32768 -o rom816.bin rom816.hex
-</code>
 ^File^Description|
@@ Line 53: / Line 89: @@
 |{{:boards:sbc:65c816_ecb_sbc:gal-u16.pld|U16 GAL Source}} |GAL (U16) V1|
 |{{:boards:sbc:65c816_ecb_sbc:gal-u17.pld|U17 GAL Source}} |GAL (U17) V1|
+|{{:boards:sbc:65c816_ecb_sbc:gal_jed.zip|:boards:sbc:65c816_ecb_sbc:gal_jed.zip}} |Compiled JED files for GALs|
 |{{:boards:sbc:65c816_ecb_sbc:sbc65816_bom.xlsx|BOM}} |BOM (excel format) – ensure U6 is 74HCT!!|
 |{{:boards:sbc:65c816_ecb_sbc:sbc816rom.zip|SBC816ROM}} |Native Mode ROM monitor source code (Based on Supermon 816)|
-__[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:65c816_ecb_sbc:system.jpg|{{  :boards:sbc:65c816_ecb_sbc:system.jpg?direct&800x616}}]]__
+ERRTA, and user notes
+<font 11pt/Calibri,sans-serif;;inherit;;inherit>BorutK has been building the 65c816PCB and has made the following observations while bringing his board up . .</font>
+  * <font 11pt/Calibri,sans-serif;;inherit;;inherit>U16 gal20v8 and U7 74xx14 must be fast! In order to get the board to run Borut needed a 7ns GAL in U16 and U7 needed to be a 74F14 or 74ALS14.</font><font 11pt/Calibri,sans-serif;;inherit;;inherit>There was a problem where sometimes U5 would latch in some spurious high addresses which should not be there and that screwed the ram writes. The scream test would work, but 1 out of 3 ram accesses would be wrong.</font><font 11pt/Calibri,sans-serif;;inherit;;inherit>The reason was that U7E which inverts the CPUCLK to latch the high addresses was delaying too much. WDC datasheet says that BA will hold max 10ns after the clock flank goes high.</font>
+Also, he suggested the following if we ever do a respin of the board
+  * <font 9.5pt/Calibri,sans-serif;;inherit;;inherit>There should be better Vcc and GND planes needed between power connector and CPU (measured 0.7 - 0.8V Vcc spikes on clock switch @ 4Mhz)</font> * <font 9.5pt/Calibri,sans-serif;;inherit;;inherit>To fix this, he in an additional tantalum cap on power connector, a 100nf filter cap directly under CPU and two wires directly from power connector to cpu.</font>
+  * <font 9.5pt/inherit;;inherit;;inherit>Add A15 to ROM socket to enable use of 27512 (i like to use Winbond W27E512, they are cheap, come in 45ns version and are EEPROMS)</font>* <font 9.5pt/Calibri,sans-serif;;inherit;;inherit>Then it should be possible to change GAL equations to have a mirror of whole EPROM on some high address, as a small rom disk.</font>
+  * <font 9.5pt/Calibri,sans-serif;;inherit;;inherit>It seems that CS equations should also incorporate & ( VPA # VDA ) term, because 65C816</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>sometimes</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>puts</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>some</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>erroneous</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>addresses</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>on</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>the</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>address</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>bus</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>. This only happens on some specific conditions, it only happens on read, during indexed access an index 8bit rollover, due to internal 8 bit addition of addresses.</font> * <font 9.5pt/Calibri,sans-serif;;inherit;;inherit>At the moment U16 has only one free pin, so it might require going to 22V10 gal</font>
+  * <font 9.5pt/Calibri,sans-serif;;inherit;;inherit>Add ((VPA&VDA)&!MON_ROM) in GAL, connect to LS06 (OC) and over switch to NMI for single step.</font> * <font 9.5pt/Calibri,sans-serif;;inherit;;inherit>Similar approach was used in KIM1 computer.</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>The idea is that VPA=1 & VDA=1 signals OPcode fetch. If this is connected with a "Single step" switch to NMI it will trigger a Non maskable interrupt.</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>The CPU then jumps into monitor rom and dumps the registers. Next GO will start a new OPcode fetch and the cycle repeats.</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>To disable NMI during ROM execution !MON_ROM term is added.</font>
+  * <font 9.5pt/Calibri,sans-serif;;inherit;;inherit>if at all possible a 6522 VIA would be great, to have some additional peripheral on this board, since place is scarce, maybe in a PLCC format.</font><font 9.5pt/Calibri,sans-serif;;inherit;;inherit>VIA ports could be connected to a 26pin header in a manner similar to 8255 on zeta board, and might even enable use of a ParPortProp.</font>
+[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?tok=aebc3d&media=https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/sbc/65c816_ecb_sbc/system.jpg|{{  https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/sbc/65c816_ecb_sbc/system.jpg?direct&1080x832  |www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_boards_sbc_65c816_ecb_sbc_system.jpg}}]]
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