65C816 ECB SBC
I have had this idea rattling around in my head for a 65816 ECB SBC for some time now – and I had some free time on a family trip, so I put form to that thought. With a tremendous amount of assistance from John Coffman, I am pleased to say the the 65C816 SBC is a reality.
I will be adding more documentation to this page, as the project progresses – I hope to get firmware running on the board with support for the RBC disk controllers and Video adapters.
For now, we have a ROM monitor (based on Supermon 816– big thank you to BCS technology for making this software free to use/modify) working that supports the following commands:
A — Assemble code C — Compare memory regions D — Disassemble code F — Fill memory region (cannot span banks) G — Execute code (stops at BRK) H — Search (hunt) memory region J — Execute code as a subroutine (stops at BRK or RTS) L -- Load a Motorola format S28 file into memory M — Dump & display memory range R — Dump & display 65C816 registers T — Copy (transfer) memory region> — Modify up to 32 bytes of memory ; — Modify 65C816 registers
I am working on building out hardware support in the BIOS. At the moment only on board Serial Read/Write, DISKIO V3 Floppy, VGA3 Video and PS/2 Keyboard and On board RTC is supported. The OS supports the FAT12 file system (8.3 file names) and will boot from a floppy disk. A ported version of 6502 ehBasic (emulation mode only) is also included in the software download.
Long Term I intend to have support in the BIOS for:
- DISKIO V3 (HDD/FDD) - Floppy interface working and supported by BIOS and OS, HDD and ATAPI interfaces in progress
- VGA3 - Supported in both Memory mapped and port access mode by both BIOS and OS
- Dual SD – future
- DualDMA Disk (HDD/FDD) – future
- Color VDU – future
- VDU – future
- SCG – future
The memory map is:
000000 - 007FFF On Board RAM 008000 - 00FDFF On Board RAM or ROM - ROM can be software selectable to 32K or a choice of a 8 or 16K bank - bank size selectable in GAL equations 00FE00 - 00FE06 16550 UART 00FE07 - FE07 RTC & ROM SIZE SELECTION FLAG 00FE08 - 00FEFF Mapped to Z80 ports for ECB bus boards (IO) 00FF00 - 00FFFF BIOS and Hardware Vectors 00FF00 - 00FF70 Native mode jump table 00FF71 - 00FFEF Emulation Mode jump table 00FFF0 - 00FFFF Hardware Vectors 010000 - 07FFFF On Board RAM 080000 - FFFFFF Open to ECB Bus Current BIOS functions are: Long Call: FF00 LOUTCH - output char in A to serial port FF03 LINCH - get char from serial port into A FF08 LINCHW - get char from serial port into A (Blocking) FF0C LINITDISK - initialize storage device (supports DISKIO V3 Floppy only at the moment) FF10 LREADDISK - Read Disk Sector into BIOS buffer (supports DISKIO V3 Floppy only at the moment) FF14 LWRITEDISK - write Disk Sector from BIOS buffer (supports DISKIO V3 Floppy only at the moment) FF18 LWRITERTC - Write value to RTC register FF1C LREADRTC - Read value from RTC register Short Call: FF71 OUTCH - output char in A to serial port FF74 INCH - get char from serial port into A FF77 INCHW - get char from serial port into A (Blocking) FF7A INITDISK - initialize storage device (supports DISKIO V3 Floppy only at the moment) FF7D READDISK - Read Disk Sector into BIOS buffer (supports DISKIO V3 Floppy only at the moment) FF80 WRITEDISK - write Disk Sector from BIOS buffer (supports DISKIO V3 Floppy only at the moment) FF83 WRITERTC - Write value to RTC register FF86 READRTC - Read value from RTC register
The ROM file can be built with the Western Design Centers tool set that is available for free from the WDC web site. http://wdc65xx.com/wdctools-download-2/
Note that while these tools do have a couple of bugs that require careful attention to syntax, they appear to be generally usable. Both an assembler and C compiler are available.
All of the source files as well as an assembled binary are in the ZIP file.
|KiCad Schematic||Schematic V1|
|PDF Schematic||Schematic V1|
|PDF Board||Board V1|
|U13 GAL source||GAL (U13) V1|
|U16 GAL Source||GAL (U16) V1|
|U17 GAL Source||GAL (U17) V1|
|:boards:sbc:65c816_ecb_sbc:gal_jed.zip||Compiled JED files for GALs|
|BOM||BOM (excel format) – ensure U6 is 74HCT!!|
|SBC816ROM||Native Mode ROM monitor source code (Based on Supermon 816)|
ERRTA, and user notes
BorutK has been building the 65c816PCB and has made the following observations while bringing his board up . .
- U16 gal20v8 and U7 74xx14 must be fast! In order to get the board to run Borut needed a 7ns GAL in U16 and U7 needed to be a 74F14 or 74ALS14.There was a problem where sometimes U5 would latch in some spurious high addresses which should not be there and that screwed the ram writes. The scream test would work, but 1 out of 3 ram accesses would be wrong.The reason was that U7E which inverts the CPUCLK to latch the high addresses was delaying too much. WDC datasheet says that BA will hold max 10ns after the clock flank goes high.
Also, he suggested the following if we ever do a respin of the board
- There should be better Vcc and GND planes needed between power connector and CPU (measured 0.7 - 0.8V Vcc spikes on clock switch @ 4Mhz) * To fix this, he in an additional tantalum cap on power connector, a 100nf filter cap directly under CPU and two wires directly from power connector to cpu.
- Add A15 to ROM socket to enable use of 27512 (i like to use Winbond W27E512, they are cheap, come in 45ns version and are EEPROMS)* Then it should be possible to change GAL equations to have a mirror of whole EPROM on some high address, as a small rom disk.
- It seems that CS equations should also incorporate & ( VPA # VDA ) term, because 65C816sometimesputssomeerroneousaddressesontheaddressbus. This only happens on some specific conditions, it only happens on read, during indexed access an index 8bit rollover, due to internal 8 bit addition of addresses. * At the moment U16 has only one free pin, so it might require going to 22V10 gal
- Add ((VPA&VDA)&!MON_ROM) in GAL, connect to LS06 (OC) and over switch to NMI for single step. * Similar approach was used in KIM1 computer.The idea is that VPA=1 & VDA=1 signals OPcode fetch. If this is connected with a “Single step” switch to NMI it will trigger a Non maskable interrupt.The CPU then jumps into monitor rom and dumps the registers. Next GO will start a new OPcode fetch and the cycle repeats.To disable NMI during ROM execution !MON_ROM term is added.
- if at all possible a 6522 VIA would be great, to have some additional peripheral on this board, since place is scarce, maybe in a PLCC format.VIA ports could be connected to a 26pin header in a manner similar to 8255 on zeta board, and might even enable use of a ParPortProp.