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boards:ecb:zilog-peripherals:start [2018/07/20 10:05]
b1ackmai1er [Schematics]
boards:ecb:zilog-peripherals:start [2021/06/29 08:33] (current)
b1ackmai1er
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 ===== Pictures ===== ===== Pictures =====
  
-[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?tok=6b48cf&media=https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/ecb/zilog-peripherals/zilogperipheral1.jpg|{{https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/ecb/zilog-peripherals/zilogperipheral1.jpg?direct&400x300  |www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_boards_ecb_zilog-peripherals_zilogperipheral1.jpg}}]]+{{https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/ecb/zilog-peripherals/gallery/zilogperipheral1.jpg?nolink&500x375|www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_boards_ecb_zilog-peripherals_gallery_zilogperipheral1.jpg}}
  
 [[:boards:ecb:zilog-peripherals:gallery|Photo gallery]] [[:boards:ecb:zilog-peripherals:gallery|Photo gallery]]
- 
-=====   ===== 
- 
-=====   ===== 
  
 ===== Specifications ===== ===== Specifications =====
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 ===== Acknowledgments ===== ===== Acknowledgments =====
  
-The ECB ZILOG Peripherals board is based on a design presented in c't magazine in 1985 "Datenverkehr - Die I/O-Karte fur den ECB-Bus" by Georg Umback. The original documentation for this project can be seen here: {{:boards:ecb:zilog-peripherals:zp_dart_sio_ct8504.pdf|:boards:ecb:zilog-peripherals:zp_dart_sio_ct8504.pdf}}+The ECB ZILOG Peripherals board is based on a design presented in c't magazine in 1985 "Datenverkehr - Die I/O-Karte fur den ECB-Bus" by Georg Umback. The original documentation for this project can be seen here: [[:boards:ecb:zilog-peripherals:development|]]
  
-Andrew Lynch designed the current version with David Giles and Douglas Goodall assisting with testing on the SBC V1 & V2 respectively.+Andrew Lynch designed the Retrobrew version with David Giles and Douglas Goodall assisting with testing on the SBC V1 & V2 respectively. 
 + 
 +===== Version ===== 
 + 
 +The following documentation and files describe version 2 which has not been manufactured and tested as at 29/11/2019. Version 2 adds a jumper to bridge CTC counter 2 and 3 so that CTC counter 2 can be used as a prescaler. The serial headers connectors have been reconfigured to the IBM PC standard. A reset configuration jumper has been added to allow selection of either KONTRON or Legacy (N8VEM) reset method. 
 + 
 +Details on prior versions can be can be found [[:https:www.retrobrewcomputers.org:doku.php?id=boards:ecb:zilog-peripherals:changes|here.]]
  
 ===== Hardware Documentation ===== ===== Hardware Documentation =====
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 ==== Schematics ==== ==== Schematics ====
  
-{{:boards:ecb:zilog-peripherals:zilog_peripherals-schematic.pdf|:boards:ecb:zilog-peripherals:zilog_peripherals-schematic.pdf}}+{{:boards:ecb:zilog-peripherals:v2:zilog_peripherals-schematics-2.0_002.pdf|:boards:ecb:zilog-peripherals:v2:zilog_peripherals-schematics-2.0_002.pdf}}
  
 ==== Board Layout ==== ==== Board Layout ====
  
-{{:boards:ecb:zilog-peripherals:zilog_peripherals-full-board.pdf|:boards:ecb:zilog-peripherals:zilog_peripherals-full-board.pdf}}+{{:boards:ecb:zilog-peripherals:v2:zilog_peripherals-board-2.0_002.pdf|:boards:ecb:zilog-peripherals:v2:zilog_peripherals-board-2.0_002.pdf}} 
 + 
 +==== KiCad Files ==== 
 + 
 +{{:boards:ecb:zilog-peripherals:v2:zilog_peripherals-kicad-2.0_002.zip|:boards:ecb:zilog-peripherals:v2:zilog_peripherals-kicad-2.0_002.zip}}
  
 ==== PCB Gerber files ==== ==== PCB Gerber files ====
  
-[[:builderpages:b1ackmai1er:ecb_zilog_peripherals_pcb|Untested ECB Zilog Peripherals Gerber files ]]+{{:boards:ecb:zilog-peripherals:v2:zilog_peripherals-gerbers-2.0_002.zip|:boards:ecb:zilog-peripherals:v2:zilog_peripherals-gerbers-2.0_002.zip}}
  
-[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?tok=716cd0&media=https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/builderpages/b1ackmai1er/ecb_zilog_peripherals.png|{{https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/builderpages/b1ackmai1er/ecb_zilog_peripherals.png?direct&710x436}}]]+==== PCB Parts List ==== 
 + 
 +{{:boards:ecb:zilog-peripherals:v2:zilog_peripherals-partlist-2.002.txt|:boards:ecb:zilog-peripherals:v2:zilog_peripherals-partlist-2.002.txt}}
  
 ==== Connectors ==== ==== Connectors ====
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 ===== Hardware Documentation ===== ===== Hardware Documentation =====
- 
  
 ==== Board address ==== ==== Board address ====
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 Visual guide for I/O address setting: Visual guide for I/O address setting:
  
-{{https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/ecb/zilog-peripherals/zilog-peripherals-jumpers.png?nolink&800x406}}+[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?tok=41fbe6&media=https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/ecb/zilog-peripherals/zilog-peripherals-jumpers.png|{{https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/ecb/zilog-peripherals/zilog-peripherals-jumpers.png?direct&800x406}}]]
  
 ==== Chip address ==== ==== Chip address ====
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 |   \\ 19200|   \\ 614400|   \\ /16|   \\ 8-10| |   \\ 19200|   \\ 614400|   \\ /16|   \\ 8-10|
 |   \\ 38400|   \\ 1228800|   \\ /16|   \\ 9-11| |   \\ 38400|   \\ 1228800|   \\ /16|   \\ 9-11|
 +
 +More information on baud rate selection and limitations can be found [[:boards:ecb:zilog-peripherals:clock-divider|here.]]
  
 Next the Z80-DART/SIO's clock pins need to be connected to PHI_X using header X6. For the fixed baud rate jumper pins 3-5 or 5-7 for channel A and 8-10 for channel B of header X6 (as in the photo). This assumes the above recommended modification has been made. Next the Z80-DART/SIO's clock pins need to be connected to PHI_X using header X6. For the fixed baud rate jumper pins 3-5 or 5-7 for channel A and 8-10 for channel B of header X6 (as in the photo). This assumes the above recommended modification has been made.
  
-==== Serial leads ==== +==== Serial Leads ====
- +
-The Zilog peripheral board header layouts are different to the other boards in the N8VEM range so custom cables must be made. Here is an example - the Z80-DART/SIO doesn't provide a DSR input so it uses DCD instead. Ring Indicator is also not used.+
  
 |   \\ X3 / X7 pin|   \\ Signal|   \\ DB-9M|   \\ DB-9F|   \\ Note| |   \\ X3 / X7 pin|   \\ Signal|   \\ DB-9M|   \\ DB-9F|   \\ Note|
-|   \\ 1|   \\ GND|   \\ 5|   \\ 5|   | +|   \\ 1|  DCD in|       | 
-|   \\ 2|   \\ GND|   \\ 5|   \\ 5|   | +|   \\ 2|  DSR|       | 
-|   \\ 3|   \\ /Tx out|   \\ 3|   \\ 2|   | +|   \\ 3|   \\ /Rx in|       | 
-|   \\ 4|   \\ DCD in|   \\ 6 / 1|   \\ 4|   | +|   \\ 4|   \\ RST out|       | 
-|   \\ 5|   \\ /Rx in|   \\ 2|   \\ 3|   | +|   \\ 5|   \\ /Tx out|       | 
-|   \\ 6|   \\ DTR out|   \\ 4|   \\ 6 / 1|   | +|   \\ 6|   \\ CST int|       | 
-|   \\ 7|   \\ RST out|   \\ 7|   \\ 8|   | +|   \\ 7|   \\ DTR out|       | 
-|   \\ 8|   \\ n/c|   \\ n/c|   \\ n/c|   | +|   \\ 8|   \\ RI|       | 
-|   \\ 9|   \\ CTS in|   \\ 8|   \\ 7|   |+|   \\ 9|   \\ GND|       |
 |   \\ 10|   \\ n/c|   \\ n/c|   \\ n/c|   | |   \\ 10|   \\ n/c|   \\ n/c|   \\ n/c|   |
  
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 The Z80-CTC provides four counter / timer channels. Channel 0 can be used as the baud rate clock source for the Z80-DART/SIO channel A. Channel 1 can be used for the Z80-DART/SIO channel B baud rate clock source. All four channels are available on header X4. The Z80-CTC provides four counter / timer channels. Channel 0 can be used as the baud rate clock source for the Z80-DART/SIO channel A. Channel 1 can be used for the Z80-DART/SIO channel B baud rate clock source. All four channels are available on header X4.
  
-The channels can also be used to provide mode 2 vectored interrupts for non-Zilog I/O (e.g. the UART on the N8VEM Z80 SBC). To do this put the channel into counter mode with a preset value of 1. When the trigger input is activated by the interrupt source, the counter will decrement to zero and cause an interrupt to the CPU with the vector provided by the Z80-CTC.+The channels can also be used to provide mode 2 vectored interrupts for non-Zilog I/O (e.g. the UART on the Z80 SBC V2). To do this put the channel into counter mode with a preset value of 1. When the trigger input is activated by the interrupt source, the counter will decrement to zero and cause an interrupt to the CPU with the vector provided by the Z80-CTC. 
 + 
 +Channel 2 & 3 can be configured to provide a 50Hz interrupt which can facilitate implementing multi-tasking system. This required setting appropriate clock dividers, configuration jumpers and software modes. 
 + 
 +  * Assuming 4.9152Mhz crystal 
 +  * Jumper X5 pins 15-16 and pins 9-11 
 +  * Jumper X5 pin 3 (PHI_X) to X4 pin 7 (CTC_TG2) 
 +  * Jumper P1 (on v1 board jumper X4 pin 8 (CTC_ZC2) to X4 pin 9 (CTC_TG3) 
 +  * Configure the interrupt vector. 
 +  * Configure channel 3 to divide by 256 
 +  * Configure channel 4 to divide by 48 and interrupt. 
 +  * Refer to ROMWBW ctc.asm driver for example. 
 + 
 +To enable the CTC, ROMWBW must be rebuilt with the following custom configuration added: 
 + 
 +SBC_std_cust.asm 
 + 
 +<code> 
 +CTCENABLE     .SET     TRUE    ; ENABLE ZILOG CTC SUPPORT 
 +CTCBASE       .SET     $B0     ; CTC BASE I/O ADDRESS 
 +</code> 
 + 
 +Correct operation of the 50Hz interrupt timer can be confirmed with the TIMER.COM: 
 + 
 +<code> 
 +TIMER /C 
 +</code> 
 + 
 +[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?media=boards:ecb:zilog-peripherals:ctctimer.gif|{{:boards:ecb:zilog-peripherals:ctctimer.gif?direct&392x108}}]]
  
 ==== Z80-PIO ==== ==== Z80-PIO ====
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 For this section I will assume the base address of the board is B0h, the oscillator module at U8 is 4.9152MHz. On X5 there are jumpers between 7-8 and 15-16 to give a baud rate of 9600. On X6 jumper pins 3-5 and 8-10 to put the baud rate clock to the Z80-DART/SIO. If available use a frequency counter to measure 153600Hz at pins 13, 14 and 27 of the Z80-DART/SIO. For this section I will assume the base address of the board is B0h, the oscillator module at U8 is 4.9152MHz. On X5 there are jumpers between 7-8 and 15-16 to give a baud rate of 9600. On X6 jumper pins 3-5 and 8-10 to put the baud rate clock to the Z80-DART/SIO. If available use a frequency counter to measure 153600Hz at pins 13, 14 and 27 of the Z80-DART/SIO.
  
-  * Testing the Z80-CTC+==== Testing the Z80-CTC ====
  
 On X6 put a jumper on pins 2-4 to put the 153600Hz signal to channel 0. Using DBGMON send the following to the Z80-CTC. (Text in <font inherit/inherit;;#000000;;inherit>blue is what you type)</font> On X6 put a jumper on pins 2-4 to put the 153600Hz signal to channel 0. Using DBGMON send the following to the Z80-CTC. (Text in <font inherit/inherit;;#000000;;inherit>blue is what you type)</font>
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 The first command sets channel 0 as a counter, the second sets the count value to 256. The output on pin 7 of the Z80-CTC should be 600Hz (153600 / 256). The third and fourth commands set channel 1 as a timer which divides the system clock by 65536. Given my setup has the CPU running at 4MHz the output on pin 8 of the Z80-CTC should be a bit over 61Hz (4000000/65536). The outputs are not a square wave but a series of pulses and were too short to be picked up by my ancient logic probe. However they measured correctly on my frequency counter. An oscilloscope would be handy as well. The first command sets channel 0 as a counter, the second sets the count value to 256. The output on pin 7 of the Z80-CTC should be 600Hz (153600 / 256). The third and fourth commands set channel 1 as a timer which divides the system clock by 65536. Given my setup has the CPU running at 4MHz the output on pin 8 of the Z80-CTC should be a bit over 61Hz (4000000/65536). The outputs are not a square wave but a series of pulses and were too short to be picked up by my ancient logic probe. However they measured correctly on my frequency counter. An oscilloscope would be handy as well.
  
-  * Testing the Z80-DART/SIO+==== Testing the Z80-DART/SIO ====
  
 I am using a SIO/0 on my board. The DART uses the same register layout except the synchronous stuff is missing. \\ I am using a SIO/0 on my board. The DART uses the same register layout except the synchronous stuff is missing. \\
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 Once the loopback test is successful then take out the jumper in X7, put in your carefully constructed serial lead and try it with a terminal. Once the loopback test is successful then take out the jumper in X7, put in your carefully constructed serial lead and try it with a terminal.
  
-  * Testing the Z80-PIOs+==== Testing the Z80-PIOs ====
  
-After reset the Z80-PIOs will have their ports set to mode 1 (all inputs). Using the monitor to read the four ports at $B8$B9$BC and $BD (i.e.I B8) will read the values on the pins. With nothing connected to headers X1 and X2 my Z80-PIOs read all zeros. A clip lead from the 5 to any I/O pin will show up as a different value when the port is read. \\  \\ +After reset the Z80-PIOs will have their ports set to mode 1 (all inputs). Using the monitor to read the four ports at 0xB80xB90xBC and 0xBD (i.e.I B8) will read the values on the pins. With nothing connected to headers X1 and X2 my Z80-PIOs read all zeros. A clip lead from the 5 to any I/O pin will show up as a different value when the port is read. 
-At this stage you should have a functioning Zilog Peripheral Board. Combined with the N8VEM Z80-SBC you now have enough serial ports, timers and parallel ports to create a working MP/M system. Any takers?+ 
 +A simple register test program is available (base address 0xB0): {{:boards:ecb:zilog-peripherals:2piotst.zip|:boards:ecb:zilog-peripherals:2piotst.zip}} 
 + 
 + \\ 
 +At this stage you should have a functioning Zilog Peripheral Board. Combined with the SBC V2 you now have enough serial ports, timers and parallel ports to create a working MP/M system. Any takers?
  
 ==== Using the Z80-PIO with a Centronics printer. ==== ==== Using the Z80-PIO with a Centronics printer. ====
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 ==== Resources ==== ==== Resources ====
  
-{{filelist>*&style=table&tableheader=1&tableshowdate=1&tableshowsize=1}}+[[:https:www.retrobrewcomputers.org:doku.php?id=boards:ecb:zilog-peripherals:datasheets|Datasheets]] 
 + 
 +\\
  
  
boards/ecb/zilog-peripherals/start.1532095516.txt.gz · Last modified: 2018/07/20 10:05 by b1ackmai1er
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