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boards:ecb:zilog-peripherals:start [2019/11/29 09:22]
b1ackmai1er [Serial leads]
boards:ecb:zilog-peripherals:start [2020/01/29 06:13]
b1ackmai1er [Z80-CTC]
Line 183: Line 183:
 |   \\ X3 / X7 pin|   \\ Signal| ​  \\ DB-9M| ​  \\ DB-9F| ​  \\ Note| |   \\ X3 / X7 pin|   \\ Signal| ​  \\ DB-9M| ​  \\ DB-9F| ​  \\ Note|
 |   \\ 1|  DCD in|   ​| ​  ​| ​  | |   \\ 1|  DCD in|   ​| ​  ​| ​  |
-|   \\ 2|  DSR \\  ​|   \\ 5|   \\ 5|   | +|   \\ 2|  DSR|   ​| ​  ​| ​  | 
-|   \\ 3|   \\ /Rx in|   \\ 3|   \\ 2|   |+|   \\ 3|   \\ /Rx in|   ​| ​  ​| ​  |
 |   \\ 4|   \\ RST out|   ​| ​  ​| ​  | |   \\ 4|   \\ RST out|   ​| ​  ​| ​  |
 |   \\ 5|   \\ /Tx out|   ​| ​  ​| ​  | |   \\ 5|   \\ /Tx out|   ​| ​  ​| ​  |
 |   \\ 6|   \\ CST int|   ​| ​  ​| ​  | |   \\ 6|   \\ CST int|   ​| ​  ​| ​  |
 |   \\ 7|   \\ DTR out|   ​| ​  ​| ​  | |   \\ 7|   \\ DTR out|   ​| ​  ​| ​  |
-|   \\ 8|   \\ RI|   \\  ​|   \\  ​|   |+|   \\ 8|   \\ RI|   ​| ​  ​| ​  |
 |   \\ 9|   \\ GND|   ​| ​  ​| ​  | |   \\ 9|   \\ GND|   ​| ​  ​| ​  |
 |   \\ 10|   \\ n/c|   \\ n/c|   \\ n/c|   | |   \\ 10|   \\ n/c|   \\ n/c|   \\ n/c|   |
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   * Configure channel 4 to divide by 48 and interrupt.   * Configure channel 4 to divide by 48 and interrupt.
   * Refer to ROMWBW ctc.asm driver for example.   * Refer to ROMWBW ctc.asm driver for example.
 +
 +To enable the CTC, ROMWBW must be rebuilt with the following custom configuration added:
 +
 +SBC_std_cust.asm
 +
 +<​code>​
 +CTCENABLE ​    ​.SET ​    ​TRUE ​   ; ENABLE ZILOG CTC SUPPORT
 +CTCBASE ​      ​.SET ​    ​$B0 ​    ; CTC BASE I/O ADDRESS
 +</​code>​
 +
 +Correct operation of the 50Hz interrupt timer can be confirmed with the TIMER.COM:
 +
 +<​code>​
 +TIMER /C
 +</​code>​
 +
 +[[https://​www.retrobrewcomputers.org/​lib/​exe/​fetch.php?​media=boards:​ecb:​zilog-peripherals:​ctctimer.gif|{{:​boards:​ecb:​zilog-peripherals:​ctctimer.gif?​direct&​392x108}}]]
  
  
boards/ecb/zilog-peripherals/start.txt · Last modified: 2020/01/29 06:13 by b1ackmai1er
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