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boards:ecb:zilog-peripherals:changes [2019/11/29 06:49]
b1ackmai1er created
boards:ecb:zilog-peripherals:changes [2019/11/29 07:08] (current)
b1ackmai1er [Version 1]
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 ===== Version 1 ===== ===== Version 1 =====
  
-In version 1 the Zilog peripheral board header layouts are different to the other boards in the ECB and are shown below. ​ Custom cables must be made. For example - the Z80-DART/​SIO doesn'​t provide a DSR input so it uses DCD instead. Ring Indicator is also not used.+In version 1 the Zilog peripheral board header layouts are different to the other boards in the ECB and are shown below. Custom cables must be made. For example - the Z80-DART/​SIO doesn'​t provide a DSR input so it uses DCD instead. Ring Indicator is also not used.
  
 Version 2 aligns the board with standard IBM PC standard. Version 2 aligns the board with standard IBM PC standard.
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 |   \\ 9|   \\ CTS in|   \\ 8|   \\ 7|   | |   \\ 9|   \\ CTS in|   \\ 8|   \\ 7|   |
 |   \\ 10|   \\ n/c|   \\ n/c|   \\ n/c|   | |   \\ 10|   \\ n/c|   \\ n/c|   \\ n/c|   |
 +
 +==== Schematics ====
 +
 +{{:​boards:​ecb:​zilog-peripherals:​zilog_peripherals-schematic.pdf|:​boards:​ecb:​zilog-peripherals:​zilog_peripherals-schematic.pdf}}
 +
 +==== Board Layout ====
 +
 +{{:​boards:​ecb:​zilog-peripherals:​zilog_peripherals-full-board.pdf|:​boards:​ecb:​zilog-peripherals:​zilog_peripherals-full-board.pdf}}
 +
 +==== KiCad Files ====
 +
 +{{:​boards:​ecb:​zilog-peripherals:​ecb_zilog_peripherals.zip|:​boards:​ecb:​zilog-peripherals:​ecb_zilog_peripherals.zip}}
 +
 +==== PCB Gerber files ====
 +
 +{{:​boards:​ecb:​zilog-peripherals:​ecb_zilog_peripherals_gerbers.zip|ECB Zilog Peripherals Gerber files }}
  
 \\ \\
  
  
boards/ecb/zilog-peripherals/changes.txt · Last modified: 2019/11/29 07:08 by b1ackmai1er
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