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The ECB-4PIO is a digital input and output interface board. It's a 100x160mm Eurocard Kontron compatible board designed to work with the Z80 SBC V2 processor board.
<note>The R03 board layout is not correct. It has the power and ground lines reversed for the Z80 PIO chips and will result in the destruction of the PIO chips. See the Errata page for more information. R02 board layouts are currently not available.</note>
Revision 3 board:
Revision 3 board (port 90h Kontron reset):
The ECB-4PIO was developed by Wolfgange Kabatzke based on a similar design by Janich & Klass.
Z80 PIO Operating modes
<note>The board length is 160.782mm and may require adjusting in order for the Eurocard connected to fit.</note>
This pinout is compatible to jk82-PIO-WRAP by Janich & Klass.
Each PIO has a 26-pin connector associated with the following pin assignments:
The board occupies 16 I/O addresses. Jumper S1 defines the start address. Jumpers for A4 to A7 of S1 define the upper 4 bits of the start address. Refer to the address guidelines to identify available address for your system.
A4 7-8 POSN 4
A5 5-6 POSN 3
A6 3-4 POSN 2
A7 1-2 POSN 1
The default settings for the ECB-4PIO is a base address of 0x20h:
A4 7-8 ON
A5 5-6 OFF
A6 3-4 ON
A7 1-2 ON
For address setting is important to note that "ON" is a zero and "OFF" is a one (The switches are set to GND!).
Jumper S2 is the board reset select option. Jumper position 1 (1-2) to set legacy mode. Jumper position 2 (3-4) to select Kontron mode. All board in your system should be set to have matching settings. Check the SBC V2 Errata notes if you are intending to run on Kontron compatibility mode.
3-4 set to /RESET (C31, N8VEM)
1-2 set to /PWRCLR (C26, Kontron compatibility)
Each Z80 PIO chip uses four addresses out of the sixteen I/O addresses decoded by the ECB-4PIO board. The upper 4 bits of the address are set by jumpers for A4 to A7 using S1. The mapping of the addresses to the PIO's is shown below, assuming a base address 0x20:
Attention! The assignment of A0 and A1 changed to the following: A0 → B/~A, A1 → C/~D. This is conform to the ZILOG-datasheets and other applications all around the world. At the JP82-PIO WRAP this was changed.
R1-R12 4.7K Resistor
C1-C12 100nF Ceramic
C20-C24 100uF Electrolytic
S1 2×2 pin header
S2 2×4 pin header
P 1 VG-96 connector (a,b,c)
P 2-5 Header 4 x 26pin (2 x 13pin)
Socket: 3 x 14pin, 2 x 16pin, 2 x 20pin, 4 x 40pin.
<note>R1-R12 are shown as 1K in the schematics.</note>
The four PIO are able to use vector interrupts and are prioritized in a daisy chain. The daisy chain is connected to a carry-look-ahead logic, so that the processing delay is in the range of 10 to 20ns.
BUS —> PIO 0 —> PIO 1 —→ PIO 2 —> PIO 3 —→ BUS
IEI IEO IEI IEO IEI IEO IEI IEO
Through pull-up resistors of the IEO PIO-0, PIO-1, PIO-2 and PIO-3 is a proper function of the daisy chain be guaranteed even if not all 4 PIO are fitted. PIO's must be fitted in order PIO-0 to PIO-1, -2, -3 in order to maintain the daisy chain.
The Bus acknowledge Daisy-Chain BAI/BAO is hard wired on the ECB-4PIO since the board is only for the ECB bus (compatible to) KONTRON.
The ECB-4PIO is not currently supported by ROMWBW or UNABIOS.
Test software is available here: