Table of Contents
General characteristics of the ECB-4PIO-board
The ECB-4PIO board contains 4 Z80A-PIOand the complete Bus-Control-Logic for the ECB-Systembus conform to KONTRON.
The technical data of the ECB-4PIO-board in brief:
· 4 Z80A-PIOA
o The PIO data signals and READY and STROBE are for each of the two data ports connected on a 26pin header. The pinout of this connector is compatible to jk82-PIO-WRAP by Janich & Klass.
· Single Eurocard with ECB-bus
o ECB-4PIO is full IM2-interruptible. The bus control logic allows RETI-detection for the internal PIO. IEI and IEO are wired to look ahead. Even with a partial assembly the IEI/IEO Daisy Chain is fully preserved.
· Power consumption at typical 4MHz 400mA (at 5V)
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|printing_ecb-4pio-r02-brd.pdf||729.5 KiB||2015/11/01 04:07|
|printing_ecb-4pio-r02-sch.pdf||179.0 KiB||2015/11/01 04:06|
|printing_ecb-4pio-r03-brd.pdf||663.8 KiB||2015/11/01 04:07|
|printing_ecb-4pio-r03-sch.pdf||197.3 KiB||2015/11/01 04:07|
The four PIO are able to realize vectorinterrupt and are prioritized in a daisy chain. The daisy chain is connected to a carry-look-ahead logic, so that the processing delay is in the range of 10 to 20ns.
BUS —> PIO 0 —> PIO 1 —→ PIO 2 —> PIO 3 —→ BUS
IEI IEO IEI IEO IEI IEO IEI IEO
Through pull-up resistors of the IEO PIO-0, PIO-1, PIO-2 and PIO-3 is a proper function of the daisy chain be guaranteed even if not all 4 PIO are fitted.
Pin assignment of parallel ports
Each PIO is a 26-pin connector associated with the following assignment:
Signal Pin Pin Signal
B7 1 2 A7
B6 3 4 A6
B5 5 6 A5
B4 7 8 A4
B3 9 10 A3
B2 11 12 A2
B1 13 14 A1
B0 15 16 A0
+5V 17 18 GND
BSTB 19 20 ASTB
BRDY 21 22 ARDY
NC 23 24 NC
NC 25 26 NC
This pinout is compatible to jk82-PIO-WRAP by Janich & Klass.
Jumper Assignment (at R03 changed to jumper)
Jumper S1 board address
7-8 x x A4
5-6 x x A5
3-4 x x A6
1-2 x x A7
Jumper S2 RESET-select
3-4 set to /RESET (C31, N8VEM)
1-2 set to /PWRCLR (C26, Kontron-konform)
Address settings of the I / O ports
The ECB-4PIO board occupies 16 I / O addresses, the upper 4 bits ofthe address are set by DIP switches for A4 to A7 (see assignment of S1)
The address assignment looks like this:
Attention! The assignment of A0 and A1 changed to the following: A0 → B/~A, A1 → C/~D. This is conform to the ZILOG-datasheets and other applications all around the world. At the JP82-PIO WRAP this was changed.
A7 A6 A5 A4 A3 A2 A1 A0 (Hex) Funktion
x x x x 0 0 0 0 (20) PIO 0 DATA Kanal A
x x x x 0 0 0 1 (21) PIO 0 DATA Kanal B
x x x x 0 0 1 0 (22) PIO 0 CTRL Kanal A
x x x x 0 0 1 1 (23) PIO 0 CTRL Kanal B
x x x x 0 1 0 0 (24) PIO 1 DATA Kanal A
x x x x 0 1 0 1 (25) PIO 1 DATA Kanal B
x x x x 0 1 1 0 (26) PIO 1 CTRL Kanal A
x x x x 0 1 1 1 (27) PIO 1 CTRL Kanal B
x x x x 1 0 0 0 (28) PIO 2 DATA Kanal A
x x x x 1 0 0 1 (29) PIO 2 DATA Kanal B
x x x x 1 0 1 0 (2A) PIO 2 CTRL Kanal A
x x x x 1 0 1 1 (2B) PIO 2 CTRL Kanal B
x x x x 1 1 0 0 (2C) PIO 3 DATA Kanal A
x x x x 1 1 0 1 (2D) PIO 3 DATA Kanal B
x x x x 1 1 1 0 (2E) PIO 3 CTRL Kanal A
x x x x 1 1 1 1 (2F) PIO 3 CTRL Kanal B
The information in the column “(Hex)” refer to the default address settings (see 4.3)!
For address setting is important to note that “ON” a zero and “OFF” means a one (The switches are set to GND!).
The Busaknowledge-Daisy-Chain BAI/BAO is on the ECB-4PIO static connected. Since this PCB only for the ECB bus (compatible to) KONTRON was developed, the implementation is static.
Default settings of the jumpers
On delivery of an assembled circuit board, the jumpers are set as follows:
7-8 5-6 3-4 1-2
„ON“ „OFF“ „ON“ „ON“
A4 A5 A6 A7
That means I / O base address of the board: 20H
IC 1 74LS07 Socket: 3 x 14pin
IC 2 74LS08 2 x 16pin
IC 3 74LS27 2 x 20pin
IC 4 74LS541 4 x 40pin
IC 5 74LS85
IC 6 74LS245
IC 7 74LS139
IC 8, 9, 11,12 Z80A-PIO
R 12x 4k7
C 12 x 100nF RM 2,5
S 1 DIL-Switch 8pin
S 2 DIL-Switch 4pin
P 1 VG-96 connector (a,b,c)
P 2-5 Header 4 x 26pin (2 x 13pin)
Differences between the ECB and 4PIO jk82-PIO-WRAP
Between the two PCB are differences, not logically, but in design.
There layout of ECB-4PIO requires a rearrangement of IC8 - IC10 or PIO-0 - PIO-3 (jk82-PIO-WRAP) to IC8 to PIO, 11, 9, 12 and PIO-0 to PIO-3:
IC8 PIO-0 IC8 PIO-0
IC9 PIO-1 IC11 PIO-2
IC10 PIO-2 IC9 PIO-1
IC11 PIO-3 IC12 PIO-3
The order in the daisy chain is amended IC numbers are not influenced by there arrangement.
By the replacement of some component types and the use of a new IC with open collector (IC10), Component numbering was reassigned:
IC1 74LS85 IC5 74LS85
IC2 74LS139 IC7 74LS139
IC3 74LS21 IC10 74LS21
IC4 74LS08 IC2 74LS08
IC5 74LS27 IC3 74LS27
IC6 74LS243 IC4 74LS541
IC7 74LS245 IC6 74LS245, 74LS645
This was necessary because the driver IC6 (74LS243) of the circuit of jk82-PIO-WRAP by IC4 (74LS541) has been replaced. So now the AB2, AB3, IEI (by bus) and Ф(by bus) driven, as these signals are shared.
Furthermore, all /INT-outputs of PIO-0 PIO-3 are coupled via a resistor to +5 V (due to open-drain) and a driver of IC1 (74LS07) decouples the PIO from the ECB (Now are all PIO undriven with any signal on the ECB bus).
The DIL switch for the bridge /BAI to /BAO of jk82-PIO-WRAP is on the ECB-4PIO replaced by a fixed bridge.
The rest of the circuit was not changed. Es There is simply no longer WRAP box.
Changes from R01 to R02
New is in R0.2 the DIP-Switch S2. With the help of S2 we can use the KONTRON-conform Reset-Signal /PWRCLR (ECB C26) as RESET for PIO or like N8VEM the Signal /RESET (ECB C31)
Changes from R02 to R03:
- replacement from DIP-switches to jumper
- A0 to B/~A
- A1 to C/~D
- optimization of the look-ahead-carry logic