The ECB-4MEM memory board is a 4Megabyte memory board. It is a 100x160mm Eurocard Kontron compatible board designed to work with the ECB SBC-188 board.

The board, known as 4MEM, may contain up to 8 x 512Kb memory chips. Options include: dual battery backup for SRAM, Flash memory instead of SRAM, or Flash memory in addition to SRAM.

The following discussion assumes the board is entirely SRAM.

The SBC-188, based on the Intel 80C188 microprocessor, has a 1Mb address space; i.e., an address bus of 20 bits. One half of this address space (512K) is SRAM on the SBC-188 itself, which occupies the low memory addresses. There is also a boot and BIOS ROM of from 32K to 256K located at the top of memory. The 4MEM board is intended to fill the addresses from 80000h to the lowest ROM address (say, F0000h) in pages of size 16K. Pages may be permanently mapped, or managed as EMM (Expanded Memory) using driver code accessible through the EMM BIOS call on int 67h.

The ECB bus is expanded to accommodate the SBC-188 by adding four additional address bits on pins suggested by Kontron, the German firm which originated the bus. The 4MEM board uses only the ECB bus signals on connector rows a) and c), plus the four added address bits on those rows.

The most recent version of project files are here: :boards:ecb:4mem:ecb_4mem-004.zip

The 4MEM board may contain anywhere from 1 to 8 memory chips of size 512K. A fully stuffed board has 8 x 512K = 4Mb of memory organized as 255 pages of size 16K. One page is always reserved as the “INVALID” page, meaning it is neither readable nor writable. Hence, page numbers on a board range from 0 to 254, with page 255 used (in hardware) as the Invalid page.

The 20 bit address space of the SBC-188 is divided into 64 x 16K logical pages. The first 32 of these are occupied by the on-board SRAM, and the highest several are used by the BIOS ROM. Approximately 28 to 30 page slots, addressed by A19..A14 (six bits) may be assigned to any available page on a 4MEM board. Multiple Logical Pages may refer to the same Physical Page.

4MEM board initialization on the SBC-188 should map the first 32 Logical Pages to the Invalid Page. Likewise for Logical Pages in the ROM address space.

Each 4MEM board occupies two I/O addresses on the ECB bus. The address is selectable through 7 address switches on the board. The two I/O addresses are:

PAGE at Board Base address + 0 R/W
ADDR at Board Base address + 1 W only

Two I/O writes are needed to set up a single page mapping. The first write is to ADDR. Bits 5 to 0 in the output byte correspond to the Logical Page address bits A19 to A14 where a page mapping is to be established. The second write is to DATA. Bits 7 to 0 of the output byte select a Physical Page on the 4MEM board to which the Logical Address range previously specified is to be mapped. If the output byte to DATA is 255(0FFh), then the Logical Page is specified as Invalid. The 4MEM board does not respond to read or write requests within Logical Pages that have been marked as Invalid.

If multiple 4MEM boards are in use, the same Logical Page should not be assigned to a Physical Page on more than one board at the same time. If two 4MEM boards were to respond to the same read request at a given address, the resulting read would be unpredictable.

At power up, the contents of the 4MEM page map are unpredictable. In order to prevent contention on the data bus from unwanted page mappings, the 4MEM board contains an overall Enable flip-flop. The ECB bus /RESET signal clears this flip-flop, so at power-up the board is disabled with respect to all memory requests. Power-up initialization code should set up the entire memory map. It is suggested that all Logical Pages initially be marked “Invalid” (i.e., mapped to Page 255). The board is enabled by an I/O read of the PAGE register. Once the Enable flip-flop is set, it can only be cleared by another system-wide RESET.

Assuming a board is purely SRAM, then one or two batteries may be used to provide backup. Battery voltages should be in the range of 2.5 to 3.6 volts. Battery backup is controlled by three pin jumper J5 and two pin jumper J6. Battery backup from the backplane ECB bus, VBAT on position c24, is selected by shorting J5:1-2. If no battery backup is selected by J5, then it should be shorted J5:2-3. A second battery connection is provided on J6. The battery is connected with a 2 pin connector, pin 1 is positive(+), and pin 2 is negative(-). If no battery is connected to J6, then the pins should be shorted J6:1-2.

It is possible to connect an external battery to J5 using a 2 pin connector. In this case pin 2 is connected to positive(+) and pin 3 is connected to negative(-). In this case of 2 external batteries, VBAT is not used.

See Caution below if any Flash ROM is used.

The 4MEM board may be stuffed with SRAM, Flash ROM, or a mixture of both. The board is divided into two banks of 2Mb; i.e., four sockets each for 512K chips. Each bank is separately jumpered. Only one type of memory may be installed in a particular bank. The lower bank is chip locations U0 to U3, and the upper bank is chip locations U4 to U7. The jumper block controlling the lower bank is J12, and the jumper block controlling the upper bank is J34. The jumper blocks are identical.

For SRAM the corresponding bank jumper block is connected Jxy:1-3,2-4. For Flash ROM the corresponding bank jumper block is connected Jxy:3-5,4-6.

The 4MEM board has no jumper settings that directly allow the use of CMOS EPROM. Wiring of a special socket is necessary to use EPROM. All memory chips should be of size 512K bytes to be compatible with the memory mapping scheme.

If the board is stuffed with a mix of SRAM and Flash ROM, all battery backup should be disabled; viz., J5:2-3, J6:1-2. Better yet, the DS1210 chip should be removed, and the socket jumpered 1-8 & 5-6.

The 4MEM board is compatible with the SBC-188 production board, SBC-188 revision 1.0 or later. The SBC-188 prototype (rev. 00.4) board does not export enough bus signals to be compatible.

Any number of 4MEM boards may be plugged into the ECB bus as long as they occupy different I/O addresses for programming the memory map. Just be sure that software adheres to the Restrictions detailed above.

John Coffman
20-Nov-2010
09-Jan-2011
08-Oct-2011