This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
boards:ecb:2s1p:start [2020/01/12 11:06]
rcini [2S1P - Dual Serial/Single EPP Parallel Interface]
boards:ecb:2s1p:start [2021/10/10 00:08] (current)
Line 5: Line 5:
 {{https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/ecb/2s1p/ecb_2s1p_001.png?nolink&800x484|ECB 2S1P Board Plot}} {{https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/ecb/2s1p/ecb_2s1p_001.png?nolink&800x484|ECB 2S1P Board Plot}}
 +{{https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/ecb/2s1p/img_6854.jpg?nolink&800x1067|EBC 2S1P board as-built.}}
 ===== Overview ===== ===== Overview =====
Line 14: Line 15:
 As a point of note, the board is NOT compatible with the ST16C552 due to a different pin arrangement. As a point of note, the board is NOT compatible with the ST16C552 due to a different pin arrangement.
 +===== Construction Notes =====
 +==== Resistor Arrays ====
 +The resistor arrays (RN501, RN502) that are part of the RC damper circuit for the parallel port are __isolated__ resistors, not the more common bussed resistor arrays that most builders have in stock. They are also an uncommon value (27 ohms) for your typical RetroBrew build. The schematic shows this difference, but if you go straight by the BOM, that difference isn't clear.
 ===== Errata ===== ===== Errata =====
 None in version 1.0-001 (the first production run). None in version 1.0-001 (the first production run).
 +===== Software =====
 +The UAR/T used is a derivative of the Intel 8251 UAR/T so most basic code will run without significant modification. To use with MS-DOS on the SBC-188, TSR (terminate and stay resident) drivers are required to provide replacement BIOS functions (none of the BIOSes, including the latest BIOS-050, do not have any code to support the board). Additionally, most DOS programs assume that the serial and parallel ports live at specific I/O port addresses and are interrupt-capable. On versions of the SBC-188 prior to version 3, the interrupt system doesn't conveniently allow for interrupt-driven serial ports such as the 2S1P, so the 2S1P has to be run in "polled" mode. It's expected that version 3 of the SBC-188 will have a usable/trappable interrupt that can be connected to the 2S1P to allow for most software to work; the I/O port and interrupt selection allocation will still be an issue but that's easier to deal with.
 +The software should be considered "beta" quality.
 ===== Resources ===== ===== Resources =====
Line 26: Line 36:
 |{{:boards:ecb:2s1p:ecb_2s1p-1.0-001_pcb.pdf|ECB 2S1P-1.0-001_pcb.pdf}} |500Kb|2019-12-27| |{{:boards:ecb:2s1p:ecb_2s1p-1.0-001_pcb.pdf|ECB 2S1P-1.0-001_pcb.pdf}} |500Kb|2019-12-27|
 |{{:boards:ecb:2s1p:ecb_2s1p-1.0-001.zip|ECB 2S1P-1.0-001_design.zip}} |2.1Mb|2020-01-12| |{{:boards:ecb:2s1p:ecb_2s1p-1.0-001.zip|ECB 2S1P-1.0-001_design.zip}} |2.1Mb|2020-01-12|
 +|{{:boards:ecb:2s1p:ecb_driver_rel01.zip|ECB 2S1P_driver_rel01.zip}} |39Kb|2020-01-17|
 \\ \\
boards/ecb/2s1p/start.1578845162.txt.gz · Last modified: 2020/01/12 11:06 by rcini
Driven by DokuWiki Recent changes RSS feed Valid CSS Valid XHTML 1.0