Welcome to the RBC build page of Trick-1. There is something about computers that you can open up, design new bits for, work on and fix that I really like. It was exactly that in the form of an Apple II europlus that got me hooked on computing back in the 1980's. I have a varied background in electronics and computing. For me it is both work and occasional recreation when time permits.
The recreation aspect can be slow, glaciers move faster, and is broadly around
Built but yest to be tested
Pending final parts
To be built
This is a rather bad photo but shows my initial setup in an ABS Rack Case. This is now in a metal EuroCard Rack case (photo pending)
September 2017 Update
Well after a big session I now have my RBC running a custom ROMWBW 2.4.8 with the following hardware. See the forum posts around DISKIO and CVDU for information on what was done there to make it all work.
The following is the current setup
Transputer's a 5 second Introduction
A Transputer is a CPU originally designed by INMOS in the late 1980's. The CPU was designed with parallel computing in mind. Defining features of a Transputer are
What is a TRAM
A TRAM is basically a standard carrier for an INMOS Transputer and the circuit for its function such as Compute with memory, SCSI, ethernet, serial etc. The following link provides some information regards the TRAM specification. http://www.transputer.net/tn/29/tn29.html#x1-50003.1
Example of TRAM can be seen plugged into the Tram Carrier Card below.
TRAM's are silly expensive on ebay! So probably not the place to start if you don't have any. Much better to wait for the ECB Transputer CPU Card.
Basic Transputer System
A basic Transputer system consists
the basic setup is
[Host CPU] <→ [BUS] <→ [Transputer Link Interface] <→ [Transputer Network]
The HOST CPU communicates to the Transputer network via the Transputer LInk Interface.
ECB Transputer Link Interface (aka TLI )
This is something I want to try and bring to the community as it will allow communication from an ECB system to a Transputer network.
It is slow progress and maybe one day I will hopefully finish the board design. I have started to design the link interface leveraging the prototype board work that is already in existence and borrowing heavily from Das Transputer Buch (yes that book really is a fantastic source of information).
The link interface would allow the connection of an ECB based system to a Transputer network. The ECB Tram Carrier Card is a candidate.
Mar/17 - Design almost finalised, just need to complete the bus connections before sending to PCBWay (http://www.pcbway.com/) for the first run.
ECB TRAM Carrier Card (aka 4TC2 )
The idea here is to create a simple ECB card that can support 1-4 INMOS TRAM's.
Have started work but original design needs some revision to make it more aligned with standard practices.
Have finalised a design
I sent the files to PCBway (http://www.pcbway.com/) for manufacture. Once tested will put this up in the ECB boards section with all the right gerber files.
Gerber files for version 0.4 of the board :builderpages:trick-1:4tc2v0.4.zip
Jan/17 - Boards arrived from PCBway, well packed, professionally made and in cool red! Have assembled and tested 1 unit. Some minor layout, screen print and design issues to resolve but they work!
Feb/17 - Version 0.4 of the board is now confirmed fully working however a number of design modifications have been made and Version 0.5 of the board is pending.
v0.4 plugged into Axel @ Geekdot's Apple II Transputer Link Card
Proof of life. Simple BASIC program using PEEK/POKE to interact and confirm that there is a Transputer connected.
The following is the image of the version 0.4 board with 4 INMOS TRAM's installed.
Jul/17 - Version 0.5 of the board has been finalised and sent for manufacture (http://www.pcbway.com).
Jul/17 - Version 0.5 boards have arrived.
The following files are what have been sent. Please note that this version has had some modifications and re-routing from v0.4 of the board and as yet have not been tested.
ECB Transputer CPU Card (TCPU)
This card is in initial design phase but is aiming to be
This is ideal for those who want to put a Transputer in their system but maybe cannot get hold of a TRAM module.
ECB Transputer CPU Card -TCPUv0.1
6/7/2017 Have decided that the first development version will be just the Transputer, link connections, power and mandatory support circuit all other pins from the Transputer will be broken out into a header so that I can experiment with memory and other peripherals.
KiCAD and Gerber Files :builderpages:trick-1:ecbtcpu_version_0.1.zip
7/7/2017 Version 0.1 files have been sent to manufacture at (http://www.pcbway.com)…
Jul/17 0.1 boards have arrived….
Sep/17 Version 0.1 board finally built, tested and working!.
errata so far
The following shows the current state. You can see the 74LS04 on a vero board behind the main board. Also the brown wire jumper down to the breakout where the link speed connections ended up. Plugged into my IIe running the basic test code and those magic words “32 BIT TRANSPUTER FOUND”
next step is to build out some memory options
ECB Transputer CPU Card -TCPUv0.2
In planning but will be looking to fix the errors of version 0.1 and add the first go at memory.
Also considering adding the bus to link interface circuit so that the board will work standalone in an ECB system but that might wait until version 0.3
Version 0.2 of the TCPU board arrived late December and as usual I got caught up in other things. Building this simple board was been slow progress and was finished in late February. Unfortunately the memory didn't turn up for another month….
Here is the blank board.
Here is the board finally completed and connected to the PC for testing.
Initial tests failed to the CPU, after a while I realised I had tied one of the control lines (Analyze) to ground for some mad reason when I was re-drawing a section of the schematic, out with the knife and some bodging later I was able to see the Transputer. However I could not find any memory. About two months worth of frustration later I have finally managed to identify and talk to the memory, although not reliably or quickly. The issues:
The following shows the current test setup
Any how as of late May I am now getting the following which shows that it is at least identifying the memory. However it is not talking to it reliably.
(sorry they are on an angle)
As can be seen lots of errors and lots of different memory sizes for Transputer number 9 which is the one that we are testing. off to read more manuals and recall all that I have lost about T states
The Transputer CPUs (T4xx/T8xx) have a programmable three-cycle memory interface. Through jumper configurations on the board they can support a variety of DRAM and SRAM. More information can be found in the reference manual http://www.transputer.net/ibooks/72-trn-203-02/tdata3rd.pdf .I am now working through the various combinations to determine the best configuration for the memory I am using as the it is not being reliably identified.
I am also yet to get the bank 1 operating. I will do this once I get bank 0 working properly.
So there we have it - some progress.
Next iteration I am going to
ECB Manual Cross Bar Switch (MCBS)
This card has been designed but is yet to be manufactured for testing. This is mainly because I have not built enough ECB based Transputer cards to warrant doing so. In theory it is a manual version of the INMOS IMSC004 Cross Bar Switch. Obviously not software configurable.
The card allows the connection of all unused links from other ECB Transputer boards via a single ribbon cable and then allow for the link configuration to be set with jumper cables. This will allow for maximum configuration of a given set of Transputers cards from either Final version of TCPU or 4TC2v0.5 and above.
The following are the KiCAD Design and Gerber Files. I have never had this board fabricated but as you can see it is rather simple.