The ECB RAM Floppy is a 4Mb memory board designed to be used as a high speed battery backed memory disk drive.
ECB RAM Floppy was developed by Dr. Wolfgang Kabatzke. The original documentation for this project is on the n8vem-pbwiki-archive.
The current version is Revision 11. R11 is an mix of the former layout R06 with counter 74HCT4040 and R10 (ATMEL TINY 13, TLC7705), but a fixed physical sector size of 512Byte
Revision 13 is under development as of early 2016 with the main feature being PAL replacement of LS-TTL-Logic.
Some of the documentation and images below show inconsistencies in version numbers or development versions.
Schematics are available here: :boards:ecb:ramfloppy:printing_ecb-ramf-r11.sch.pdf
Board's PCB layout: :boards:ecb:ramfloppy:printing_ecb-ramf-r12.brd.pdf
Kicad files for board manufacture: :boards:ecb:ramfloppy:ecb-ramf-r11.zip
In order to optimize the performance of an ECB-based N8VEM computer, I wanted to design a storage subsystem with the following criteria:
For the optimization of working with the ECB N8VEM-computer, I was looking for a fast storage medium like a hard drive is in use, but should not be so expensive, and which may receive its data and buffered.
It is important to note the difference between a RAM DISK and a RAM Floppy. A RAM disk (also Ramdrive) is a virtual disk and temporary in memory (RAM) of a computer. A RAM disk is a storage subsystem generally implemented using volatile RAM, sometimes made persistent through the use of a battery, and sometimes not. If the storage is not persistent, then the data will become invalid when the power is turned off.
The benefit of the RAM Disk is the fast access speed. Since it is implemented in memory, access to it occurs at memory speeds and there is no latency or seem time involved. There is also no delay based on the rotational speed of the media. Because of this it´s often referred to as Virtual Memory, although some virtual memory has advanced paging and lookaside capability not addressed here. The liability with this type of storage subsystem is the volatility of the data should the power by turned off or interrupted by accident.
It is common for small RAM Disks to be implemented by allocating some portion of the processors main ram. A benefit of this is that a modest RAM Disk can be implemented without separate hardware. The liability is that it reduces the amount of main RAM in what may already be a “resource challenged” implementation. A RAM Floppy on the other hand does not use the local memory resources of the processor, but instead is implemented as an external storage subsystem, which may functionally appear as being similar to a floppy or modest hard drive. As with the RAM Drive, the RAM floppy has efficient access to the storage medium, suffering neither seek-time, latency, nor the delay of rotational media. It is therefore an efficient and expandable storage medium, which may be easily added to an already existing system. It has most of the advantages of a RAM Drive, but none of the limitation, such as the reduction of available main RAM.
It is mainly used when other physical storage media is placed too slowly or when the computer again, are not available.
Disadvantages of the RAM disk are that the relevant space to free memory, so the operating system and other programs to cache, no longer available. After a reboot of the system (eg after a crash), the contents of the RAM disk generally disappeared (except for reset-proof RAM disks). Because RAM is one of the volatile storage media, if the power supply disappears (eg when switching off) with the memory content and the ramdisk content. Therefore, on the RAM disk should be no important data is stored, unless the uninterruptible power supply to the computer is guaranteed. Should continue before turning off the computer may still be required files are backed up (eg, automated via script). Measured by the price per storage size matters this way to the more expensive storage method.
RAM disks are not to be confused with RAM floppies (like ECB-RAMF). The latter are a more hardware-based replacement for a floppy drive (for example, as a plug-in card) in older or different computer systems. There is not here used by software (driver) is a part of the memory, but a hardware used. They are physical disks and put it in principle rather precursor of Solid State Drives represent.
The result is the ECB-RAMF board, an I/O module, which almost behaves like a mass storage device (HD).
It's not similar to the RAM-Drive of the N8VEM-SBC. This is a memory which is mapped with a memory-window-technology into the address space of the Z80.
The memory of the ECB-RAMF has the following features:
The description of the module is used in this document refer to the hardware revision R1.1 Releasedate 15th July 2013. The hardware has been changed to a greater extent and is not compatible with previous version R0.6 (R0.7 as R0.6 with corrections). This is an typical process of Microcomputerdevelopment.
The actual storage media in the RAM Floppy is a collection of eight static RAMs (providing a storage capacity of 4MBytes per board).
The central parts of the assembly are the 8 pieces SRAMs with a maximum total storage capacity of 4 Mbytes on one PCB.
The maximum size of a storage device in CP/M 2.2 is 8Mbyte. The hardware of 2 PCB ECB-RAMF R1.1 can combine together “with software” to one RAM-Floppy with 8Mbyte Data-capacity.
The maximum size of a disk device under CP/M-80 v2.2 is 8MByte. In later versions this limit is much higher.
Our RAM Floppy is idea in that a normal CP/M drive can be implemented using two RAM Floppies providing the total of eight megabytes. One board can provide a smaller but still usable amount of additional fast storage.
An addressing logic, which simulates the structure of a hard disk, controls the access to the memory. On the ECB bus are usable:
The battery backup of the ECB-RAMF is a simple circuit based on conventional Diode- and circuit technology, enuring that not even go after turning off your N8VEM the information stored in the memory components of the assembly is lost. As of R1.1, this CMOS-buffering-circuit is only usable when the module is not removed from the ECB bus.
Write protection is enable manually by toggling a switch on the board. Up (write enable), Down (write protection)
S2 / JP1 Write-Protection (switch down) – Write-Enable (switch up)
Device status may be observed on three light emitting diodes as follows…
LED1A (red) display “/PROT”
LED1B (yellow) display “/Option_Bit”
LED1C (green) activity indicator read-write access to data ECB-RAMF
Functional description of the ECB RAMF (Rev 11)
block diagram ECB-RAMF R11
The maximum storage capacity of the ECB board ECB-RAMF 11 is 4 MB, but each of the 8 SRAM IC 512kByte must be equipped on the PCB. Addressing the 4 MB is calculated in the BIOS of the CPM80 from the given data by sector and track. The logic sector size of CP/M 2.2 is 128Byte, the physical sector size of ECB-RAMF 11 is 512 Byte. These data are converted in exactly the information that is pre-loaded into the address counter as the starting address. The counter done thereby completely the byte addressing within a sector, the sector address and the track addressing. The following chart shows how the address in the address space of 4 Mbytes of SRAM composed resulting from the calculated data passed by the BIOS. This figure applies to the assignment of 128Byte/Sektor.
adress-calculation of ECB-RAMF R11
Byte-Counter Byte Address (0…511 in IC12)
SecTrk-low Sector Track Address low (IC10)
SecTrk-high Sector Track Address high (IC11)
In contrast to the sector number, the Counter can not be set directly.He can only be reset to “0” by write access to one of the sector registers (on Sector-Track Address Register-Low (IC10A) or Sector-Track-Address-Register-High (IC11A)), and reading / writing to the data register (Data-Read Data Write (IC9A)) by increasing of 1.This allows a continuous stream length of one physical sector (512 bytes) of data register to read the.This mechanism allows only the high transmission speed of the assembly. The “Byte-in-Sector” counter consists of one 74HCT-IC (74HCT4040) and thus covers the 9-Bit-address space of the ECB-RAMF of 4 Mbytes. |
the clock and control signals (timing) of the 74HCT4040
Waveforms showing the clock (/CP) to output (Q)
Figure above illustrates an I/O read or I/O write operation of the Z80-CPU. During I/O operations a single wait state is automatically inserted. The reason is that during I/O operations, the time from when the IORQ signal goes active until the CPU must sample the WAIT line is very short. Without this extra state, sufficient time does not exist for an I/O port to decode its address and activate the WAIT line if a wait is required. Also, without this wait state, it is difficult to design MOS I/O devices that can operate at full CPU speed. During this wait state time, the WAIT request signal is sampled. During a read I/O operation, the /RD line is used to enable the addressed port onto the data bus just as in the case of a memory read. For I/O write operations, the /WR line is used as a clock to the I/O port. This timing is necessary to understand why IC10A and IC11A are edge triggered and how the I/O-interface controls the Byte-sector address counter. The registers IC11A and IC12A are latched with a low-high transition. The address decoding logic (IC17A, IC14A, IC13A and IC18A B) is connected to the address bus lines AB2-AB7, to /IORQ, /WR and to /M1. If the address at S1 is identical to the address in the software/firmware the outputs Y1 or Y2 are going to LOW if all signals are active. At the end of /WR those outputs are going to HIGH and the data on the databus is latched into IC10A (RAMF_AL) or IC11A (RAMF_AH). With the help of IC19D is the RESCNT-signal generated. This RES-signal must be static HIGH to reset IC12A. This state is active at the beginning of each access cycle to IC10A or IC11A. At the end the latches are filled and the RES-signal of IC12A is inactive. The latches IC10A and IC11A are only accessable when /WR is active. This circuit is good for a correct I/O-Timing and if the user takes SRAM with 55/70ns access time. If in the software is an I/O-Access to RAMF_DAT the output Y0 comes to LOW (active) state. This signal is connected to the /G-Input of IC9A and to IC16E. IC16E inverts this signal. This is necessary because IC12A is counting with a HIGH-LOW-edge on Input P1. This occurs at the end of each R/W-cycle to IC9A (RAMF_DAT). This is correct so that an Byte-address change occurs AFTER each R/W-access to the memory.
The battery backup of the contents of the memory is an important basic property ECB-RAMF a RAM floppy. Through the use of CMOS SRAM can easily implement this basic property. D1 and D2 are the “two way” power-supply for all 8 CMOS memory available and the CS-decoder IC14A and turn it around between the supply voltage VCC and B_VCMOS. The maximum value of current consumption for CMOS SRAM and some elements in the decoding logic (RN2, R4, R5, C15-C22) is 800mA. The memory IC pull in a typical operating current of 10…50mA in the access mode with pulsed / CS signals. This depends on the different types of CMOS-RAMs:
|Type||Current in operating mode||Current in sleep mode||Manufacturer|
Was the current in the buffer operation with fully equipped with the building blocks depends on the used type of SRAM. Please be careful: one PCB may use only for SRAM-power more then 600mA. This was the reason that I couldn't´t implement an power management IC with power switching for SRAM. The most IC deliver not more then 400mA.
In standard mode, the supply voltage VCC is active. The 8 CMOS-RAM are connected via D1 to VCC. The supply voltage VCC is reduced by the voltage UD1 from 5V to 4,7V as VCMOS. D1 must be a Shottky-type with current of 1A (1N5817). IC15 works as voltage supervisor. The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputer and microprocessor systems. During power-on, RESET is asserted when VDD reaches 1 V. After minimum VDD (≥2 V) is established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE)) remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time, td, is determined by an external capacitor C23: td = 2.1 × 104 × CT Where CT is in farads td is in seconds The calculation gives an value of C23 of 100nF. The threshold voltage of the used TLC7705IP is 4,55V.
A special task has IC15. I the case of “power down” the voltage VCC is switched off and VCMOS is now generated via D2 from B_VCMOS. The moment of switching is critical for CMOS-RAMS. The can lost information and there could be start unsolved write-cycles to the memory chips. In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control-support for static RAM. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. The memory circuit is automatically disabled during a power loss because in this the signal /RESET is going LOW. (In this application the TLC77xx power has to be supplied by the battery.) The TI-solution to solve this problem is shown in picture 4.6. Please be careful, in picture 4.6 is an CPU (TMS70C20). In the ECB-RAMF this IC is the RAM-Access-Decoder IC14A and the Input G1. G1 of IC14A must be “HIGH” to to give access to the RAM-IC. If the signal /IC15-R on G1 is going to LOW, the access to RAM-IC is denied. D1 and D2 must be 1A shottky diodes (1N5817).
Solution from Texas Instruments: Data Retention Power Down using Static CMOS RAMs:
The status display is realized by 3 LEDs. These three LEDs indicate as follows:
LED1A (red) display “Option Bit” LED1B (yellow) display “VDD available / not available” LED1C (green) activity indicator read-write access to data ECB-RAMF The activity indicator (LED1) indicates access to the data register with an LED. It is pure gimmick and has no effect on the function of the module. Simply put, they would leave easily. But, as the user wants to be seen whether and how the requests already running on the storage medium.
The operation is very simple. The DIR signal of the data register (I/O decoder IC13 output 11, OR addition over /RD) is connected to the INT0 pin of ATtiny13 connected. This signal changes from high to low level (falling edge) triggers an interrupt in the ATtiny13, initialize a timer which switches on and activates the LED as well. If the timer expires, then it will turn the LED off. Technically, the circuit is simpler than a retriggerable one-shot, and also takes up less space on the board.
The fuse bits of the ATtiny13 must not be programmed. The program is configured for its delivery.
The bus interface of the ECB-RAMF is performed by the ECB-bus standard from Kontron. The ECB system is an 8-bit parallel bus, which is originally designed for the Z80 microprocessor family. Since the ECB-bus is not in accordance with DIN / IEC / IEEE / … is specified, various ECB-bus pin assignments have been established in the market. The pin assignment of the ECB-RAMF corresponds to Kontron-ECB-assignment.
Peculiarities and exceptions:
* The screen surface is at ABC32 GND (GND)
* 2 power lines, Row ABC1 (electricity supply ), number ABC32 (GND)
* The backup battery is not located on the ECB-RAMF, only over the contact of the ECB-Bus A25
* Designed as ECB-bus option B
* The pins 11C (IEI), 16C (IEO) on the module are connected directly on the board
* The pins 12A (BAI) and 17A (BAO) are connected directly on the board
* Resetting of the address counter is optionally reversible:
over B_/RESET on C31 or B_/PWCLR on C26. This change was intended to operate as it were by CPU with pure Kontron standard or CPU with N8VEM standard with the RAM-floppy module. Switching is done via S3-1 (B_/PWCLR) or S3-2 (B_/RESET).
That´s why is the law: B_/RESET ^ B_/PWCLR
There is only one source may be selected The card format is ECB-PCB (100 mm × 160 mm, 3U) and two-row or three-row connector conform to DIN 41612. The data bus is bi-directionally with the driver IC IC9 (74LS245, maybe also 74LS645) is coupled. The data bus address bus and control bus are guided over the driver IC20, IC21 and IC22. These ICs are designed with a Schmitt trigger inputs and decouple the ECB-RAMF from the ECB-Bus (avoid excessive bus loads → Fan Out and Fan-in = 1)
A special feature of the IC22 Represents This driver consists of two halves, each with 4 bits. This 4-bit with Schmitt-trigger input to decouple the control signal /RD, /WR, /IORQ and /M1 from the bus can be used (IC22A). The other 4 bits (IC22B) are used to signal status of the ECB-RAMF to switch to the bus. These are programmatic evaluation.
The IC17A (74LS688) serves in conjunction with S1 and RN1 as I/O address decoder of the assembly. The 8 /CS signals for the SRAM-IC are formed from the ECB-RAMF-activation (IC17), the /CS decoder (IC15) and the CMOS buffer battery voltage monitoring (D1, D2 and IC15). The address latches (IC10A and IC11A) -are addressed and loaded by the ECB-RAMF-activation (IC17A) and the I/O-address decoder (IC13A).
|5||C1||rcl-TT2D4||1||47uF Tantalum pill|
|6||RN1,RN2||resistor-sil-SIL9||2||10k RN2, 4,7k RN1|
|11||IC19||DIP-14-300||1||74LS00N, DL000D, better 74F00|
|12||IC10,IC11||DIP-20-300||2||74LS374N, better 74F374|
|13||IC9||DIP-20-300||1||4LS245N (must be LS-TTL)|
|14||IC8,IC7,IC3,IC4,IC2,IC5,IC6,IC1||DIP-32-600||8||628512 (55ns), see notes.|
|15||IC17||DIP-20-300||1||74LS688N, DL8121D, AMZ8121|
|16||IC18||DIP-14-300||1||74LS32N, DL032D, better 74F32|
|17||IC13||DIP-16-300||1||74LS139N, better 74F139|
|18||IC21,IC20,IC22||DIP-20-300||3||74LS244N (must be LS-TTL)|
|19||IC16||DIP-14-300||1||74LS14N, DL014D, better 74F14|
|20||IC12||DIP-16-300||1||74HCT4040 (must be 74HCT)|
|24||IC14||DIP-16-300||1||74HCT138 (must be 74HCT)|
|27||Socket DIP32 8pc||8||Precision type|
|28||Socket DIP20 8pc||7||Precision type|
|29||Socket DIP16 8pc||3||Precision type|
|30||Socket DIP14 8pc||3||Precision type|
|31||Socket DIP8 8pc||2||Precision type|
CMOS devices are highly sensitive to static electricity! Keep your transport or CMOS chips on only conductive foam! All pins must be shorted.
Make sure that you connect to a grounding system before working with these modules. ESD is appropriate article in the trade. All IC with blocking capacitors are 100nF X7R-5 (0,1 uF Tantal is also ok, please be careful with polarization) provided. This is absolutely important. Otherwise there is an reduction of the functionality of the module due to EMC influence.
Down the text the assembly and the switch position of the ECB Standard-I/O-address ECB-RAMF R11 is shown. Basically, the I/O-address range will be adjusted to your taste. Keep in mind that this is reflected in the test program and drivers.
A closed switch means a 0-bit in the address specification. Here are some simple examples with board-start-address 0A0H #1 and 0A4H #2.
This definition is only for example. The real combination depends on system.
For a 4Mbyte singe-PCB system You need the addresses as follows:
RAMF_BAS EQU 0A0H ; Base address of RAMF RAMF_DAT EQU RAMF_BAS ; Data In/Out only to SRAM R/W RAMF_AL EQU RAMF_BAS 1 ; Address low for RAMF Memory Cell W RAMF_AH EQU RAMF_BAS 2 ; Address high for RAMF Memory Cell W RAMF_ST EQU RAMF_BAS 3 ; Status port R/O
For a 2 * 4MByte double-PCB system You need the addresses as follows:
RAMF_BAS1 EQU 0A0H ; Base address of RAMF#1 RAMF_DAT1 EQU RAMF_BAS1 ; Data In/Out only to SRAM R/W RAMF_AL1 EQU RAMF_BAS1 1 ; Address low for RAMF Memory Cell W RAMF_AH1 EQU RAMF_BAS1 2 ; Address high for RAMF Memory Cell W RAMF_ST1 EQU RAMF_BAS1 3 ; Status port R/O RAMF_BAS2 EQU 0A4H ; Base address of RAMF#2 RAMF_DAT2 EQU RAMF_BAS2 ; Data In/Out only to SRAM R/W RAMF_AL2 EQU RAMF_BAS2 1 ; Address low for RAMF Memory Cell W RAMF_AH2 EQU RAMF_BAS2 2 ; Address high for RAMF Memory Cell W RAMF_ST2 EQU RAMF_BAS2 3 ; Status port R/O
Since RomWBW 2.5.2. we find as first step 2 RAM-Floppies with an size of 4MB on each PCB.
Address assignment of ECB-RAMF-R11
|X||X||X||X||X||X||0||0||1-0-1||1||Read Data with CNT|
|X||X||X||X||X||X||0||0||1-0-1||1||Write Data with CNT|
|X||X||X||X||X||X||0||1||1||1-0-1||Write Address Low|
|X||X||X||X||X||X||1||0||1||1-0-1||Write Address High|
Write to Address Low or Address resets the Counter IC12A.
S4/1 close = AB2 = 0
S4/2 close = AB3 = 0
S4/3 close = AB4 = 0
S4/4 open = AB5 = 1
S4/5 close = AB6 = 0
S4/6 open = AB7 = 1
|0||0||0||0||0||1||10H||ECB Zilog Peripherals|
|0||0||0||0||1||0||20H||ECB Disk IO|
|0||0||0||0||1||1||30H||ECB Disk IO|
|0||0||0||1||0||0||40H||Preferred for PropIO|
|0||0||0||1||0||1||50H||Preferred for ECB SCG board|
|0||0||0||1||1||0||60H||Reserved for SBC V2|
|0||0||0||1||1||1||70H||Reserved for SBC V2|
|0||0||1||0||0||0||80H||Preferred for uPD7220 board|
|0||0||1||0||0||1||90H||Preferred for EF9366 VDU board|
|1||0||1||0||0||0||A0H||Preferred for ECB-RAMF R11 #1|
|1||0||1||1||0||1||A4H||Preferred for ECB-RAMF R11 #2|
|1||1||0||0||0||0||C0H||Preferred for ECB-ModPrn R0.2 #1 / #2|
|1||1||0||1||0||0||D0H||Preferred for ECB-PIO or EF9366 VDU|
|1||1||1||0||0||0||E0H||Preferred for ECB Color VDU board|
S3/1 reset the counter with signal B_/PWCLR
S3/2 reset the counter with signal B_/RESET
S3/3 /Option_Bit = 0
If the switch S2 is closed (switch down), the write protection is active. This prevents over IC18C that the CMOS memory can be described with a write access.
The switch S2 generates the signal “PROT”. About the status of port RAFECB_BAS 3, the following signals from the circuit of ECB-RAMF be imported and evaluated in the program.
DB1 /OPTION BIT
ECB “8 bit” interface connector (Row B unused). Further information here.
|ROW A Pin||ROW A Name||ROW A Description||ROW B Pin||ROW B Name||ROW B Description||ROW C Pin||ROW C Name||ROW C Description|
|a1||5V||5 volts dc||c1||5V||5 volts DC|
|a2||D5||Data line bit 5||c2||D0||Data line bit 0|
|a3||D6||Data line bit 6||c3||D7||Data line bit 7|
|a4||D3||Data line bit 3||c4||D2||Data line bit 2|
|a5||D4||Data line bit 4||c5||A0||Address 0|
|a6||A2||Address 2||c6||A3||Address 3|
|a7||A4||Address 4||c7||A1||Address 1|
|a8||A5||Address 5||c8||A8||Address 8|
|a9||A6||Address 6||c9||A7||Address 7|
|a11||/BUSRQ||bus request||c11||IEI||interrupt enable in|
|a14||c14||D1||Data line bit 1|
|a16||c16||IEO||interrupt enable out|
|a18||A14||address 14||c18||A10||address 10|
|a20||/M1||first cycle||c20||/NMI||not maskable interrupt|
|a26||c26||/PWCLR||CPU Reset (as output to ECB)|
|a27||/IORQ||in/out request||c27||A12||address 12|
|a28||/RFSH||refresh cycle||c28||A15||address 15|
|a29||A13||address 13||c29||PHI||System Clock from CPU|
|a30||A9||address 9||c30||/MREQ||memory request|
|a31||/BUSAK||bus acknowledge||c31||/RESET||cpu reset (as input from ECB)|
|a32||GND||signal ground||c32||GND||signal ground|
IC23 is an ATTINY13-20. It is easier to use a Microcontroller in the activity function as an retriggerable monoflop with external capacities and resistors. To program this use the HEX-File file here: :boards:ecb:ramfloppy:firmware:attiny.zip
As programming technology You may use PONY-Prog. Here is the link: http://www.lancos.com/prog.html
For our German and European friends … You may use a simple PCB from POLLIN and the software PONYPROG. Here is the link to the POLLIN-PCB:
ECB-RAMF support is not enabled by default in the ROMWBW for the SBC V2. A new build of ROMWBW will be required with changes to the following settings:
RFENABLE .EQU TRUE ; TRUE FOR RAM FLOPPY SUPPORT RFCNT .EQU 1 ; NUMBER OF RAM FLOPPY UNITS (MAX IS 2)
The default address is configured for board one at A0h and A4h for the second boards. If required these addresses can be reconfigured:
RF_U0IO .EQU $A0 RF_U1IO .EQU $A4
Test software can be found here: :boards:ecb:ramfloppy:firmware:raf113.zip
In subsequent versions of ECB-RAMF R2.0, the following features are planned:
After this the development is stopping … otherwise there is in the group interest to realize ECB-RAMF 3.0 with DMA-Access. Maybe…
|ecb-ramf-r11.zip||1.4 MiB||2015/11/01 02:59|
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