====== CRC65 Memory Map ======

0xF800-0xFFFF is internal ROM

0xF000-0xF7FF is internal I/O

  * 0xF000 is I2C bit bang register
  * 0xF008 is Serial status
  * 0xF009 is Serial Data register

0xE800-0xEF00 is external I/O

  * nCFCS pin is asserted when accessing 0xE800-0xEFFF
  * nCFRD and nCFWR are asserted only for 0xE800-0xEFFF AND A[5] to A[3] are zero and RDY is asserted for 3 clocks.
      * Example1, CF registers are located at 0xEE00-0xEE07 with 3 wait states
      * Example2, external I/O located at 0xEE40 has zero wait and only nCFCS is asserted
        * 1110_1xxx_xxyy_yxxx are addresses that has zero wait and only nCFCS asserted, where 'x' is 0 or 1, and one of the 'y' must be 1
        * examples are 0xE830 (1110_1000_0011_0000), or 0xEEFF (1110_1110_1111_1111), or 0xEC10 (1110_1100_0001_0000), or 0xE808 (1110_1000_0000_1000)

RAM is from 0x0 to 0xE7FF

=== I2C Bit Bang Register ===

I2C bit bang register is located at 0xF000 where data bit 0 drives SDA and data bit 1 drives SCL.  SDA is open collector with 2.4K pull up.  SCL is driven output.  At reset both SDA and SCL are high voltage level.